Rename verifySavedState to dumpSavedState. Give it a new comment.
Call it at a more appropriate point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13905 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 0f4c4bd..fbabc61 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -1180,11 +1180,10 @@
}
-/// Check the saved state filled in by saveState(), and abort if it looks
-/// wrong. Only used when debugging. FIXME: Currently it just prints out
-/// the state, which isn't quite as useful.
+/// Dump the saved state filled in by saveState() out to stderr. Only
+/// used when debugging.
///
-void PhyRegAlloc::verifySavedState () {
+void PhyRegAlloc::dumpSavedState () {
std::vector<AllocInfo> &state = FnAllocState[Fn];
int ArgNum = 0;
for (Function::const_aiterator i=Fn->abegin (), e=Fn->aend (); i != e; ++i) {
@@ -1379,16 +1378,19 @@
// Save register allocation state for this function in a Constant.
if (SaveRegAllocState) {
saveState();
- if (DEBUG_RA) // Check our work.
- verifySavedState ();
- if (!SaveStateToModule)
- finishSavingState (const_cast<Module&> (*Fn->getParent ()));
}
// Now update the machine code with register names and add any additional
// code inserted by the register allocator to the instruction stream.
updateMachineCode();
+ if (SaveRegAllocState) {
+ if (DEBUG_RA) // Check our work.
+ dumpSavedState ();
+ if (!SaveStateToModule)
+ finishSavingState (const_cast<Module&> (*Fn->getParent ()));
+ }
+
if (DEBUG_RA) {
std::cerr << "\n**** Machine Code After Register Allocation:\n\n";
MF->dump();