add support FNEG and FABS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21012 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index bb31fc7..7b976fc 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -80,10 +80,6 @@
setOperationAction(ISD::MEMSET , MVT::Other, Expand);
setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
- // We don't support these yet.
- setOperationAction(ISD::FNEG , MVT::f64 , Expand);
- setOperationAction(ISD::FABS , MVT::f64 , Expand);
-
computeRegisterProperties();
addLegalFPImmediate(+0.0);
@@ -794,7 +790,21 @@
BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
}
-
+
+ case ISD::FABS: {
+ Tmp1 = SelectExpr(N.getOperand(0));
+ assert(DestType == MVT::f64 && "trying to fabs something other than f64?");
+ BuildMI(BB, IA64::FABS, 1, Result).addReg(Tmp1);
+ return Result;
+ }
+
+ case ISD::FNEG: {
+ Tmp1 = SelectExpr(N.getOperand(0));
+ assert(DestType == MVT::f64 && "trying to fneg something other than f64?");
+ BuildMI(BB, IA64::FNEG, 1, Result).addReg(Tmp1);
+ return Result;
+ }
+
case ISD::AND: {
switch (N.getValueType()) {
default: assert(0 && "Cannot AND this type!");