Support fp64 immediate zero, this fixes only part of PR5445
because the testcase is triggering one more bug.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88674 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 9159904..af64c9f 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -134,6 +134,9 @@
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
DebugLoc DL = DebugLoc::getUnknownLoc();
+ const MachineFunction *MF = MBB.getParent();
+ const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
+
if (I != MBB.end()) DL = I->getDebugLoc();
if (DestRC != SrcRC) {
@@ -153,6 +156,13 @@
else if ((DestRC == Mips::FGR32RegisterClass) &&
(SrcRC == Mips::CPURegsRegisterClass))
BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
+ else if ((DestRC == Mips::AFGR64RegisterClass) &&
+ (SrcRC == Mips::CPURegsRegisterClass) &&
+ (SrcReg == Mips::ZERO)) {
+ const unsigned *AliasSet = TRI->getAliasSet(DestReg);
+ BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[0]).addReg(SrcReg);
+ BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[1]).addReg(SrcReg);
+ }
// Move from/to Hi/Lo registers
else if ((DestRC == Mips::HILORegisterClass) &&
@@ -163,9 +173,8 @@
(DestRC == Mips::CPURegsRegisterClass)) {
unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
BuildMI(MBB, I, DL, get(Opc), DestReg);
-
- // Can't copy this register
- } else
+ } else
+ // Can't copy this register
return false;
return true;