(or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121606 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 22efa48..f4a12ed 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -4727,16 +4727,37 @@
   // Case (1): or (and A, mask), val => ARMbfi A, val, mask
   if ((C = dyn_cast<ConstantSDNode>(N1))) {
     unsigned Val = C->getZExtValue();
-    if (!ARM::isBitFieldInvertedMask(Mask) || (Val & ~Mask) != Val)
+    if ((Val & ~Mask) != Val)
       return SDValue();
-    Val >>= CountTrailingZeros_32(~Mask);
 
-    Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
-                      DAG.getConstant(Val, MVT::i32),
-                      DAG.getConstant(Mask, MVT::i32));
+    if (ARM::isBitFieldInvertedMask(Mask)) {
+      Val >>= CountTrailingZeros_32(~Mask);
 
-    // Do not add new nodes to DAG combiner worklist.
-    DCI.CombineTo(N, Res, false);
+      Res = DAG.getNode(ARMISD::BFI, DL, VT, N0.getOperand(0),
+                        DAG.getConstant(Val, MVT::i32),
+                        DAG.getConstant(Mask, MVT::i32));
+
+      // Do not add new nodes to DAG combiner worklist.
+      DCI.CombineTo(N, Res, false);
+    } else if (N0.getOperand(0).getOpcode() == ISD::SHL &&
+               isa<ConstantSDNode>(N0.getOperand(0).getOperand(1)) &&
+               ARM::isBitFieldInvertedMask(~Mask)) {
+      // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
+      // where lsb(mask) == #shamt
+      SDValue ShAmt = N0.getOperand(0).getOperand(1);
+      unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
+      unsigned LSB = CountTrailingZeros_32(Mask);
+      if (ShAmtC != LSB)
+        return SDValue();
+      //unsigned Width = (32 - CountLeadingZeros_32(Mask)) - LSB;
+
+      Res = DAG.getNode(ARMISD::BFI, DL, VT, N1,
+                        N0.getOperand(0).getOperand(0),
+                        DAG.getConstant(~Mask, MVT::i32));
+
+      // Do not add new nodes to DAG combiner worklist.
+      DCI.CombineTo(N, Res, false);
+    }
   } else if (N1.getOpcode() == ISD::AND) {
     // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
     C = dyn_cast<ConstantSDNode>(N1.getOperand(1));