Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30763 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index f32ae5b..caa846b 100644
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -12,7 +12,7 @@
//===----------------------------------------------------------------------===//
#include "X86Subtarget.h"
-#include "X86GenSubtarget.inc"
+//#include "X86GenSubtarget.inc"
#include "llvm/Module.h"
#include "llvm/Support/CommandLine.h"
#include <iostream>
@@ -72,104 +72,33 @@
return true;
}
-static const char *GetCurrentX86CPU() {
+void X86Subtarget::DetectSubtargetFeatures() {
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
- if (GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
- return "generic";
- unsigned Family = (EAX >> 8) & 0xf; // Bits 8 - 11
- unsigned Model = (EAX >> 4) & 0xf; // Bits 4 - 7
- GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
- bool Em64T = EDX & (1 << 29);
-
union {
unsigned u[3];
char c[12];
} text;
- GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1);
- if (memcmp(text.c, "GenuineIntel", 12) == 0) {
- switch (Family) {
- case 3:
- return "i386";
- case 4:
- return "i486";
- case 5:
- switch (Model) {
- case 4: return "pentium-mmx";
- default: return "pentium";
- }
- case 6:
- switch (Model) {
- case 1: return "pentiumpro";
- case 3:
- case 5:
- case 6: return "pentium2";
- case 7:
- case 8:
- case 10:
- case 11: return "pentium3";
- case 9:
- case 13: return "pentium-m";
- case 14: return "yonah";
- case 15: return "core2";
- default: return "i686";
- }
- case 15: {
- switch (Model) {
- case 3:
- case 4:
- return (Em64T) ? "nocona" : "prescott";
- default:
- return (Em64T) ? "x86-64" : "pentium4";
- }
- }
-
- default:
- return "generic";
- }
- } else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
- // FIXME: this poorly matches the generated SubtargetFeatureKV table. There
- // appears to be no way to generate the wide variety of AMD-specific targets
- // from the information returned from CPUID.
- switch (Family) {
- case 4:
- return "i486";
- case 5:
- switch (Model) {
- case 6:
- case 7: return "k6";
- case 8: return "k6-2";
- case 9:
- case 13: return "k6-3";
- default: return "pentium";
- }
- case 6:
- switch (Model) {
- case 4: return "athlon-tbird";
- case 6:
- case 7:
- case 8: return "athlon-mp";
- case 10: return "athlon-xp";
- default: return "athlon";
- }
- case 15:
- switch (Model) {
- case 5: return "athlon-fx"; // also opteron
- default: return "athlon64";
- }
+ if (GetCpuIDAndInfo(0, &EAX, text.u+0, text.u+2, text.u+1))
+ return;
- default:
- return "generic";
- }
- } else {
- return "generic";
+ // FIXME: support for AMD family of processors.
+ if (memcmp(text.c, "GenuineIntel", 12) == 0) {
+ GetCpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
+
+ if ((EDX >> 23) & 0x1) X86SSELevel = MMX;
+ if ((EDX >> 25) & 0x1) X86SSELevel = SSE1;
+ if ((EDX >> 26) & 0x1) X86SSELevel = SSE2;
+ if (ECX & 0x1) X86SSELevel = SSE3;
+
+ GetCpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
+ HasX86_64 = (EDX >> 29) & 0x1;
}
}
X86Subtarget::X86Subtarget(const Module &M, const std::string &FS, bool is64Bit)
: AsmFlavor(AsmWriterFlavor)
, X86SSELevel(NoMMXSSE)
- , X863DNowLevel(NoThreeDNow)
, HasX86_64(false)
, stackAlignment(8)
// FIXME: this is a known good value for Yonah. How about others?
@@ -178,11 +107,7 @@
, TargetType(isELF) { // Default to ELF unless otherwise specified.
// Determine default and user specified characteristics
- std::string CPU = GetCurrentX86CPU();
-
- // Parse features string.
- ParseSubtargetFeatures(FS, CPU);
-
+ DetectSubtargetFeatures();
if (Is64Bit && !HasX86_64) {
std::cerr << "Warning: Generation of 64-bit code for a 32-bit processor "
"requested.\n";