commit ac0ed5dc082dff9ce359af5422f5b82047b4fe6b
author Chris Lattner <sabre@nondot.org> Thu Jul 08 22:41:28 2010 +0000
committer Chris Lattner <sabre@nondot.org> Thu Jul 08 22:41:28 2010 +0000
tree 7a21f121acf50636eed9bb3da33c97f9be597a7a
parent 0afbf23453a7ea2ed2705ca350ea64629852558c

add some long-overdue enums to refer to the parts of the 5-operand
X86 memory operand.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86MCCodeEmitter.cpp

diff --git a/lib/Target/X86/X86MCCodeEmitter.cpp b/lib/Target/X86/X86MCCodeEmitter.cpp
index 30054f2..94333ae 100644
--- a/lib/Target/X86/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/X86MCCodeEmitter.cpp
@@ -464,7 +464,7 @@
   case X86II::MRM4m: case X86II::MRM5m:
   case X86II::MRM6m: case X86II::MRM7m:
   case X86II::MRMDestMem:
-    NumOps = CurOp = X86AddrNumOperands;
+    NumOps = CurOp = X86::AddrNumOperands;
   case X86II::MRMSrcMem:
   case X86II::MRMSrcReg:
     if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() &&
@@ -606,7 +606,7 @@
   case X86II::MRM4m: case X86II::MRM5m:
   case X86II::MRM6m: case X86II::MRM7m:
   case X86II::MRMDestMem: {
-    unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
+    unsigned e = (isTwoAddr ? X86::AddrNumOperands+1 : X86::AddrNumOperands);
     i = isTwoAddr ? 1 : 0;
     if (NumOps > e && MI.getOperand(e).isReg() &&
         X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e).getReg()))
@@ -659,7 +659,7 @@
         // FIXME: This is disgusting.
         MI.getOpcode() != X86::LEA64r && MI.getOpcode() != X86::LEA64_32r &&
         MI.getOpcode() != X86::LEA16r && MI.getOpcode() != X86::LEA32r) {
-      switch (MI.getOperand(MemOperand+X86AddrSegment).getReg()) {
+      switch (MI.getOperand(MemOperand+X86::AddrSegmentReg).getReg()) {
       default: assert(0 && "Unknown segment register!");
       case 0: break;
       case X86::CS: EmitByte(0x2E, CurByte, OS); break;
@@ -814,9 +814,9 @@
   case X86II::MRMDestMem:
     EmitByte(BaseOpcode, CurByte, OS);
     EmitMemModRMByte(MI, CurOp,
-                     GetX86RegNum(MI.getOperand(CurOp + X86AddrNumOperands)),
+                     GetX86RegNum(MI.getOperand(CurOp + X86::AddrNumOperands)),
                      TSFlags, CurByte, OS, Fixups);
-    CurOp += X86AddrNumOperands + 1;
+    CurOp += X86::AddrNumOperands + 1;
     break;
       
   case X86II::MRMSrcReg:
@@ -832,7 +832,7 @@
     break;
     
   case X86II::MRMSrcMem: {
-    int AddrOperands = X86AddrNumOperands;
+    int AddrOperands = X86::AddrNumOperands;
     unsigned FirstMemOp = CurOp+1;
     if (HasVEX_4V) {
       ++AddrOperands;
@@ -870,7 +870,7 @@
     EmitByte(BaseOpcode, CurByte, OS);
     EmitMemModRMByte(MI, CurOp, (TSFlags & X86II::FormMask)-X86II::MRM0m,
                      TSFlags, CurByte, OS, Fixups);
-    CurOp += X86AddrNumOperands;
+    CurOp += X86::AddrNumOperands;
     break;
   case X86II::MRM_C1:
     EmitByte(BaseOpcode, CurByte, OS);