Add support for generating reg+reg preinc stores on PPC.
PPC will now generate STWUX and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 964d5a0..48feb98 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1105,7 +1105,15 @@
if (VT.isVector())
return false;
- // TODO: Check reg+reg first.
+ if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) {
+ if (isa<StoreSDNode>(N)) {
+ AM = ISD::PRE_INC;
+ return true;
+ }
+
+ // FIXME: reg+reg preinc loads
+ return false;
+ }
// LDU/STU use reg+imm*4, others use reg+imm.
if (VT != MVT::i64) {