commit b6632ba380cf624e60fe16b03d6e21b05dd07724
author Craig Topper <craig.topper@gmail.com> Sun Mar 04 10:16:38 2012 +0000
committer Craig Topper <craig.topper@gmail.com> Sun Mar 04 10:16:38 2012 +0000
tree 5b3ca53e138cd22a7b04e0e034b0a952d0972de7
parent 015f228861ef9b337366f92f637d4e8d624bb006

Use uint16_t instead of unsigned to store registers in reg classes. Reduces static data size.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151998 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/AllocationOrder.cpp

diff --git a/lib/CodeGen/AllocationOrder.cpp b/lib/CodeGen/AllocationOrder.cpp
index 1005f10..87f6431 100644
--- a/lib/CodeGen/AllocationOrder.cpp
+++ b/lib/CodeGen/AllocationOrder.cpp
@@ -41,7 +41,7 @@
   if (HintPair.first) {
     const TargetRegisterInfo &TRI = VRM.getTargetRegInfo();
     // The remaining allocation order may depend on the hint.
-    ArrayRef<unsigned> Order =
+    ArrayRef<uint16_t> Order =
       TRI.getRawAllocationOrder(RC, HintPair.first, Hint,
                                 VRM.getMachineFunction());
     if (Order.empty())