commit b6f656e6ad0719c09f953d79faca7732b89f16aa
author Evan Cheng <evan.cheng@apple.com> Sat Jul 11 06:37:27 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Sat Jul 11 06:37:27 2009 +0000
tree 5746e8b2c6876bc82cc69cbbad10ff4e8bcff310
parent c21feac46fc4ca1d34b5315954e49b1f29ab630f

80 col violation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75358 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index f7e634a..d7ba73c 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -588,8 +588,8 @@
   }
 
   if (DestRC == ARM::GPRRegisterClass)
-    AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)), DestReg)
-                                .addReg(SrcReg)));
+    AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)),
+                                        DestReg).addReg(SrcReg)));
   else if (DestRC == ARM::SPRRegisterClass)
     AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::FCPYS)), DestReg)
                    .addReg(SrcReg));