commit b9f4fa7b400836808bc3beab96482418f418f246
author Dan Gohman <gohman@apple.com> Fri Oct 03 15:45:36 2008 +0000
committer Dan Gohman <gohman@apple.com> Fri Oct 03 15:45:36 2008 +0000
tree 9019ef6d07a30709c5afbe52903a7cdfd9615cb1
parent 03ed0daeccf722920d2ee0a76eb399a487674f27

Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp

diff --git a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
index 8789b82..62bf87b 100644
--- a/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/AsmPrinter/ARMAsmPrinter.cpp
@@ -359,7 +359,7 @@
 /// immediate in bits 0-7.
 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
   const MachineOperand &MO = MI->getOperand(OpNum);
-  assert(MO.isImmediate() && "Not a valid so_imm value!");
+  assert(MO.isImm() && "Not a valid so_imm value!");
   printSOImm(O, MO.getImm(), TAI);
 }
 
@@ -367,7 +367,7 @@
 /// followed by a or to materialize.
 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
   const MachineOperand &MO = MI->getOperand(OpNum);
-  assert(MO.isImmediate() && "Not a valid so_imm value!");
+  assert(MO.isImm() && "Not a valid so_imm value!");
   unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
   unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
   printSOImm(O, ARM_AM::getSOImmVal(V1), TAI);
@@ -413,7 +413,7 @@
   const MachineOperand &MO2 = MI->getOperand(Op+1);
   const MachineOperand &MO3 = MI->getOperand(Op+2);
 
-  if (!MO1.isRegister()) {   // FIXME: This is for CP entries, but isn't right.
+  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
     printOperand(MI, Op);
     return;
   }
@@ -526,7 +526,7 @@
   const MachineOperand &MO1 = MI->getOperand(Op);
   const MachineOperand &MO2 = MI->getOperand(Op+1);
 
-  if (!MO1.isRegister()) {   // FIXME: This is for CP entries, but isn't right.
+  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
     printOperand(MI, Op);
     return;
   }
@@ -587,7 +587,7 @@
   const MachineOperand &MO2 = MI->getOperand(Op+1);
   const MachineOperand &MO3 = MI->getOperand(Op+2);
 
-  if (!MO1.isRegister()) {   // FIXME: This is for CP entries, but isn't right.
+  if (!MO1.isReg()) {   // FIXME: This is for CP entries, but isn't right.
     printOperand(MI, Op);
     return;
   }
@@ -749,9 +749,9 @@
       // Fallthrough
     case 'H': // Write second word of DI / DF reference.  
       // Verify that this operand has two consecutive registers.
-      if (!MI->getOperand(OpNo).isRegister() ||
+      if (!MI->getOperand(OpNo).isReg() ||
           OpNo+1 == MI->getNumOperands() ||
-          !MI->getOperand(OpNo+1).isRegister())
+          !MI->getOperand(OpNo+1).isReg())
         return true;
       ++OpNo;   // Return the high-part.
     }