erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index ce6afc3..5487eaa 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -75,7 +75,7 @@
Result |= 1 << i;
if (((Constant >> 8*i) & 0xFF) == 0xFF) {
// If the entire byte is set, zapnot the byte.
- } else if (LHS.Val == 0) {
+ } else if (LHS.getNode() == 0) {
// Otherwise, if the mask was previously validated, we know its okay
// to zapnot this entire byte even though all the bits aren't set.
} else {
@@ -242,7 +242,7 @@
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
- SDNode *N = Op.Val;
+ SDNode *N = Op.getNode();
if (N->isMachineOpcode()) {
return NULL; // Already selected.
}
@@ -345,7 +345,7 @@
}
case ISD::SETCC:
- if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
+ if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
unsigned Opc = Alpha::WTF;
@@ -460,7 +460,7 @@
void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
//TODO: add flag stuff to prevent nondeturministic breakage!
- SDNode *N = Op.Val;
+ SDNode *N = Op.getNode();
SDValue Chain = N->getOperand(0);
SDValue Addr = N->getOperand(1);
SDValue InFlag(0,0); // Null incoming flag value.
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 5128646..7beea3b 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -215,7 +215,7 @@
unsigned args_float[] = {
Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
- for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
+ for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
SDValue argt;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
SDValue ArgVal;
@@ -255,7 +255,7 @@
// If the functions takes variable number of arguments, copy all regs to stack
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
if (isVarArg) {
- VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
+ VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
std::vector<SDValue> LS;
for (int i = 0; i < 6; ++i) {
if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
@@ -281,7 +281,7 @@
ArgValues.push_back(Root);
// Return the new list of results.
- return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+ return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
ArgValues.size());
}
@@ -491,10 +491,10 @@
case ISD::SREM:
//Expand only on constant case
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
- MVT VT = Op.Val->getValueType(0);
- SDValue Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
- BuildUDIV(Op.Val, DAG, NULL) :
- BuildSDIV(Op.Val, DAG, NULL);
+ MVT VT = Op.getNode()->getValueType(0);
+ SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
+ BuildUDIV(Op.getNode(), DAG, NULL) :
+ BuildSDIV(Op.getNode(), DAG, NULL);
Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
return Tmp1;
@@ -504,8 +504,8 @@
case ISD::UDIV:
if (Op.getValueType().isInteger()) {
if (Op.getOperand(1).getOpcode() == ISD::Constant)
- return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
- : BuildUDIV(Op.Val, DAG, NULL);
+ return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
+ : BuildUDIV(Op.getNode(), DAG, NULL);
const char* opstr = 0;
switch (Op.getOpcode()) {
case ISD::UREM: opstr = "__remqu"; break;
@@ -522,7 +522,7 @@
case ISD::VAARG: {
SDValue Chain, DataPtr;
- LowerVAARG(Op.Val, Chain, DataPtr, DAG);
+ LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
SDValue Result;
if (Op.getValueType() == MVT::i32)
@@ -578,7 +578,7 @@
SDValue Chain, DataPtr;
LowerVAARG(N, Chain, DataPtr, DAG);
- return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).Val;
+ return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).getNode();
}