remove some uses of MachineOpCode, move getSchedClass
into TargetInstrDescriptor from TargetInstrInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45678 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index e3e54c5..3235f4a 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -207,7 +207,8 @@
} else {
SU->Latency = 0;
if (SU->Node->isTargetOpcode()) {
- unsigned SchedClass = TII->getSchedClass(SU->Node->getTargetOpcode());
+ unsigned SchedClass =
+ TII->get(SU->Node->getTargetOpcode()).getSchedClass();
InstrStage *S = InstrItins.begin(SchedClass);
InstrStage *E = InstrItins.end(SchedClass);
for (; S != E; ++S)
@@ -216,7 +217,7 @@
for (unsigned i = 0, e = SU->FlaggedNodes.size(); i != e; ++i) {
SDNode *FNode = SU->FlaggedNodes[i];
if (FNode->isTargetOpcode()) {
- unsigned SchedClass = TII->getSchedClass(FNode->getTargetOpcode());
+ unsigned SchedClass =TII->get(FNode->getTargetOpcode()).getSchedClass();
InstrStage *S = InstrItins.begin(SchedClass);
InstrStage *E = InstrItins.end(SchedClass);
for (; S != E; ++S)