commit bc3a5378d0854f352da38ad3574409103220fc9d
author Nate Begeman <natebegeman@mac.com> Fri Nov 19 08:01:16 2004 +0000
committer Nate Begeman <natebegeman@mac.com> Fri Nov 19 08:01:16 2004 +0000
tree 9be51588a954597d07a0bf555de05186f8227b7a
parent fa1af1344910ee975f50ffdddf605c26f80ef016

Eliminate another 6k register copies that the register allocator would just
coalesce out of hbd.  Speeds up compilation by 2% (0.6s)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17987 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/PowerPC/PPC32ISelSimple.cpp

diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 3fc72f9..c4babe0 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -3013,7 +3013,8 @@
     ConstantSInt *offset = GEPMap[GEPI].offset;
 
     if (Class != cLong) {
-      unsigned TmpReg = makeAnotherReg(I.getType());
+      unsigned TmpReg = LoadNeedsSignExtend(I) ? makeAnotherReg(I.getType())
+                                               : DestReg;
       if (indexReg == 0)
         BuildMI(BB, ImmOpcode, 2, TmpReg).addSImm(offset->getValue())
           .addReg(baseReg);
@@ -3021,8 +3022,6 @@
         BuildMI(BB, IdxOpcode, 2, TmpReg).addReg(indexReg).addReg(baseReg);
       if (LoadNeedsSignExtend(I))
         BuildMI(BB, PPC::EXTSB, 1, DestReg).addReg(TmpReg);
-      else
-        BuildMI(BB, PPC::OR, 2, DestReg).addReg(TmpReg).addReg(TmpReg);
     } else {
       indexReg = (indexReg != 0) ? indexReg : getReg(offset);
       unsigned indexPlus4 = makeAnotherReg(Type::IntTy);
@@ -3820,7 +3819,7 @@
         indexReg = getReg(remainder, MBB, IP);
         remainder = 0;
       }
-    } else {
+    } else if (!remainder->isNullValue()) {
       unsigned TmpReg = makeAnotherReg(Type::IntTy);
       emitBinaryConstOperation(MBB, IP, indexReg, remainder, 0, TmpReg);
       indexReg = TmpReg;
@@ -3835,12 +3834,19 @@
   // destination register.
   unsigned TargetReg = getReg(GEPI, MBB, IP);
   unsigned basePtrReg = getReg(Src, MBB, IP);
-  if (indexReg != 0) { 
-    unsigned TmpReg = makeAnotherReg(Type::IntTy);
-    BuildMI(*MBB, IP, PPC::ADD, 2, TmpReg).addReg(indexReg).addReg(basePtrReg);
+
+  if ((indexReg == 0) && remainder->isNullValue())
+    RegMap[GEPI] = basePtrReg;
+
+  if (!remainder->isNullValue()) {
+    unsigned TmpReg = (indexReg == 0) ? TargetReg : makeAnotherReg(Type::IntTy);
+    emitBinaryConstOperation(MBB, IP, basePtrReg, remainder, 0, TmpReg);
     basePtrReg = TmpReg;
   }
-  emitBinaryConstOperation(MBB, IP, basePtrReg, remainder, 0, TargetReg);
+  if (indexReg != 0) { 
+    BuildMI(*MBB, IP, PPC::ADD, 2, TargetReg).addReg(indexReg)
+      .addReg(basePtrReg);
+  }
 }
 
 /// visitAllocaInst - If this is a fixed size alloca, allocate space from the