Refine Cell's i64 constant generation code to cover more constants where the
upper and lower 32-bits are the same (in addition to 0 and -1 previously.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47985 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/CellSPU/immed64.ll b/test/CodeGen/CellSPU/immed64.ll
index f92cdf4..7ef3d76 100644
--- a/test/CodeGen/CellSPU/immed64.ll
+++ b/test/CodeGen/CellSPU/immed64.ll
@@ -1,6 +1,6 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
; RUN: grep lqa %t1.s | count 13
-; RUN: grep il %t1.s | count 21
+; RUN: grep il %t1.s | count 22
; RUN: grep shufb %t1.s | count 13
; RUN: grep 65520 %t1.s | count 1
; RUN: grep 43981 %t1.s | count 1
@@ -57,6 +57,10 @@
ret i64 -1 ;; IL
}
+define i64 @i64_const_10() {
+ ret i64 281470681808895 ;; IL 65535
+}
+
; 0x4005bf0a8b145769 ->
; (ILHU 0x4005 [16389]/IOHL 0xbf0a [48906])
; (ILHU 0x8b14 [35604]/IOHL 0x5769 [22377])