commit bed2946a96ecb15b0b636fa74cb26ce61b1c648e
author Anton Korobeynikov <asl@math.spbu.ru> Mon Apr 16 18:10:23 2007 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Mon Apr 16 18:10:23 2007 +0000
tree 52a39df658d308bd7dfb4f04479139d23c149c73
parent 892299ccf41e9b3726b1a9f297e47ce636b197ca

Removed tabs everywhere except autogenerated & external files. Add make
target for tabs checking.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36146 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 6058be1..2b0450b 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -53,8 +53,8 @@
   case ARM::MOVr:
   case ARM::tMOVr:
     assert(MI.getNumOperands() == 2 && MI.getOperand(0).isRegister() &&
-	   MI.getOperand(1).isRegister() &&
-	   "Invalid ARM MOV instruction");
+           MI.getOperand(1).isRegister() &&
+           "Invalid ARM MOV instruction");
     SrcReg = MI.getOperand(1).getReg();
     DstReg = MI.getOperand(0).getReg();
     return true;