| commit | c4b527ac06c8e2e7c43020a56f000a53ab1dc9de | [log] [tgz] |
|---|---|---|
| author | Evan Cheng <evan.cheng@apple.com> | Fri Jan 13 01:37:24 2012 +0000 |
| committer | Evan Cheng <evan.cheng@apple.com> | Fri Jan 13 01:37:24 2012 +0000 |
| tree | 0ca139380c834cf200bc6722f24cc6e165f296db | |
| parent | b4ee5168abd0580a29f5c9becce26e3ea7bb2b8d [diff] |
DAGCombine's logic for forming pre- and post- indexed loads / stores were being overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8