commit c65e6e4ce26caba2a6c07467ab45f74f708ffbe7
author Bill Wendling <isanbard@gmail.com> Tue Nov 25 08:19:22 2008 +0000
committer Bill Wendling <isanbard@gmail.com> Tue Nov 25 08:19:22 2008 +0000
tree 7cea45055b4aa0fb8a5a090d08ce0f866bf1652c
parent 910488477f3f5dac9f709522e708dd36a1e88779

Now with the correct type for the 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60016 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 563f84b..0a15715 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -4185,7 +4185,7 @@
       SDValue Sum = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
       MVT OType = Node->getValueType(1);
 
-      SDValue Zero = DAG.getConstant(0, OType);
+      SDValue Zero = DAG.getConstant(0, LHS.getValueType());
 
       SDValue LHSPos = DAG.getSetCC(OType, LHS, Zero, ISD::SETGE);
       SDValue RHSPos = DAG.getSetCC(OType, RHS, Zero, ISD::SETGE);