Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.
The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:
* The 's' in target data: If this is set to the minimal alignment of any
argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
example.
* The getTransientStackAlignment method. It is possible for an architecture to
have argument less aligned than what we maintain the stack pointer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/va_arg.ll b/test/CodeGen/ARM/va_arg.ll
index a54a499..7cb9762 100644
--- a/test/CodeGen/ARM/va_arg.ll
+++ b/test/CodeGen/ARM/va_arg.ll
@@ -1,10 +1,13 @@
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s
; Test that we correctly align elements when using va_arg
+; CHECK: test1:
+; CHECK-NOT: bfc
; CHECK: add r0, r0, #7
; CHECK: bfc r0, #0, #3
+; CHECK-NOT: bfc
-define i64 @f8(i32 %i, ...) nounwind optsize {
+define i64 @test1(i32 %i, ...) nounwind optsize {
entry:
%g = alloca i8*, align 4
%g1 = bitcast i8** %g to i8*
@@ -14,6 +17,25 @@
ret i64 %0
}
+; CHECK: test2:
+; CHECK-NOT: bfc
+; CHECK: add r0, r0, #7
+; CHECK: bfc r0, #0, #3
+; CHECK-NOT: bfc
+; CHECK: bx lr
+
+define double @test2(i32 %a, i32 %b, ...) nounwind optsize {
+entry:
+ %ap = alloca i8*, align 4 ; <i8**> [#uses=3]
+ %ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=2]
+ call void @llvm.va_start(i8* %ap1)
+ %0 = va_arg i8** %ap, i32 ; <i32> [#uses=0]
+ %1 = va_arg i8** %ap, double ; <double> [#uses=1]
+ call void @llvm.va_end(i8* %ap1)
+ ret double %1
+}
+
+
declare void @llvm.va_start(i8*) nounwind
declare void @llvm.va_end(i8*) nounwind