Fix decoding support for STREXD and LDREXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137356 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index d2809f0..e4d7393 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -135,6 +135,8 @@
uint64_t Address, const void *Decoder);
static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
+static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder);
static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
@@ -2481,3 +2483,24 @@
Inst.addOperand(MCOperand::CreateImm(Val));
return true;
}
+
+static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+ uint64_t Address, const void *Decoder) {
+ unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
+ unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
+ unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+
+ if (Inst.getOpcode() == ARM::STREXD)
+ if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+
+ if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
+ if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false;
+
+ if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
+ if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
+ if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+
+ return true;
+}
+
+