commit cc54e76cc67bbc9badc024ab29053602769bd255
author Owen Anderson <resistor@mac.com> Sat Aug 30 00:38:46 2008 +0000
committer Owen Anderson <resistor@mac.com> Sat Aug 30 00:38:46 2008 +0000
tree 9b98442cc75d4858fa188af45ec06ed99596a4ea
parent ea9eedb7877008082b314b7ab322843fe2d402b5

Fix an issue where a use might be selected before a def, and then we didn't respect the pre-chosen vreg
assignment when selecting the def.  This is the naive solution to the problem: insert a copy to the pre-chosen
vreg.  Other solutions might be preferable, such as:
  1) Passing the dest reg into FastEmit_.  However, this would require the higher level code to know about reg classes, which they don't currently.
  2) Selecting blocks in reverse postorder.  This has some compile time cost for computing the order, and we'd need to measure its impact.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55555 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/FastISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index 33da2b0..45920ba 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -63,6 +63,21 @@
   return Reg;
 }
 
+/// UpdateValueMap - Update the value map to include the new mapping for this
+/// instruction, or insert an extra copy to get the result in a previous
+/// determined register.
+/// NOTE: This is only necessary because we might select a block that uses
+/// a value before we select the block that defines the value.  It might be
+/// possible to fix this by selecting blocks in reverse postorder.
+void FastISel::UpdateValueMap(Instruction* I, unsigned Reg, 
+                              DenseMap<const Value*, unsigned> &ValueMap) {
+  if (!ValueMap.count(I))
+    ValueMap[I] = Reg;
+  else
+     TII.copyRegToReg(*MBB, MBB->end(), ValueMap[I],
+                      Reg, MRI.getRegClass(Reg), MRI.getRegClass(Reg));
+}
+
 /// SelectBinaryOp - Select and emit code for a binary operator instruction,
 /// which has an opcode which directly corresponds to the given ISD opcode.
 ///
@@ -90,7 +105,7 @@
                                      ISDOpcode, Op0, CI->getZExtValue());
     if (ResultReg != 0) {
       // We successfully emitted code for the given LLVM Instruction.
-      ValueMap[I] = ResultReg;
+      UpdateValueMap(I, ResultReg, ValueMap);
       return true;
     }
   }
@@ -101,7 +116,7 @@
                                      ISDOpcode, Op0, CF);
     if (ResultReg != 0) {
       // We successfully emitted code for the given LLVM Instruction.
-      ValueMap[I] = ResultReg;
+      UpdateValueMap(I, ResultReg, ValueMap);
       return true;
     }
   }
@@ -120,7 +135,7 @@
     return false;
 
   // We successfully emitted code for the given LLVM Instruction.
-  ValueMap[I] = ResultReg;
+  UpdateValueMap(I, ResultReg, ValueMap);
   return true;
 }
 
@@ -196,7 +211,7 @@
   }
 
   // We successfully emitted code for the given LLVM Instruction.
-  ValueMap[I] = N;
+  UpdateValueMap(I, N, ValueMap);
   return true;
 }
 
@@ -223,7 +238,7 @@
   if (!ResultReg)
     return false;
     
-  ValueMap[I] = ResultReg;
+  UpdateValueMap(I, ResultReg, ValueMap);
   return true;
 }
 
@@ -234,7 +249,7 @@
     unsigned Reg = getRegForValue(I->getOperand(0), ValueMap);
     if (Reg == 0)
       return false;
-    ValueMap[I] = Reg;
+    UpdateValueMap(I, Reg, ValueMap);
     return true;
   }
 
@@ -274,7 +289,7 @@
   if (!ResultReg)
     return false;
   
-  ValueMap[I] = ResultReg;
+  UpdateValueMap(I, ResultReg, ValueMap);
   return true;
 }
 
@@ -384,7 +399,7 @@
       MVT DstVT = TLI.getValueType(I->getType());
       if (SrcVT.getSimpleVT() == DstVT.getSimpleVT()) {
         if (ValueMap[I->getOperand(0)]) {
-          ValueMap[I] = ValueMap[I->getOperand(0)];
+          UpdateValueMap(I, ValueMap[I->getOperand(0)], ValueMap);
           break;
         } else
           // Unhandled operand