become more strict about when it's safe to use X86ISD::MOVLPS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112799 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 852d339..7acd893 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -5082,10 +5082,10 @@
SDValue TmpV1 = V1;
SDValue TmpV2 = V2;
- // Trivial case, when V2 is a load.
- if (TmpV2.getOpcode() == ISD::BIT_CONVERT)
+ // Trivial case, when V2 comes from a load.
+ if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::BIT_CONVERT)
TmpV2 = TmpV2.getOperand(0);
- if (TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR)
+ if (TmpV2.hasOneUse() && TmpV2.getOpcode() == ISD::SCALAR_TO_VECTOR)
TmpV2 = TmpV2.getOperand(0);
if (MayFoldLoad(TmpV2))
CanFoldLoad = true;
@@ -5095,9 +5095,9 @@
// turns into:
// (MOVLPSmr addr:$src1, VR128:$src2)
// So, recognize this potential and also use MOVLPS or MOVLPD
- if (TmpV1.getOpcode() == ISD::BIT_CONVERT)
+ if (TmpV1.hasOneUse() && TmpV1.getOpcode() == ISD::BIT_CONVERT)
TmpV1 = TmpV1.getOperand(0);
- if (MayFoldLoad(TmpV1))
+ if (MayFoldLoad(TmpV1) && MayFoldIntoStore(Op))
CanFoldLoad = true;
if (CanFoldLoad) {
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index 9dfcbc4..5540d0f 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -5829,6 +5829,13 @@
def : Pat<(v4f32 (X86Movss VR128:$src1, VR128:$src2)),
(MOVSSrr (v4f32 VR128:$src1),
(EXTRACT_SUBREG (v4f32 VR128:$src2), sub_ss))>;
+// FIXME: Instead of a X86Movss there should be a X86Movlps here, the problem
+// is during lowering, where it's not possible to recognize the load fold cause
+// it has two uses through a bitcast. One use disappears at isel time and the
+// fold opportunity reappears.
+def : Pat<(X86Movss VR128:$src1,
+ (bc_v4i32 (v2i64 (load addr:$src2)))),
+ (MOVLPSrm VR128:$src1, addr:$src2)>;
// Shuffle with MOVSD
def : Pat<(v2f64 (X86Movsd VR128:$src1, (scalar_to_vector FR64:$src2))),
@@ -5909,9 +5916,6 @@
def : Pat<(X86Movlps VR128:$src1,
(bc_v4f32 (v2f64 (scalar_to_vector (loadf64 addr:$src2))))),
(MOVLPSrm VR128:$src1, addr:$src2)>;
-def : Pat<(X86Movlps VR128:$src1,
- (bc_v4i32 (v2i64 (load addr:$src2)))),
- (MOVLPSrm VR128:$src1, addr:$src2)>;
// Shuffle with MOVLPD
def : Pat<(v2f64 (X86Movlpd VR128:$src1, (load addr:$src2))),