commit d0499af703db08b1c0c34d3c3722b06c1ae9583d
author Lauro Ramos Venancio <lauro.venancio@gmail.com> Wed Jun 06 17:08:48 2007 +0000
committer Lauro Ramos Venancio <lauro.venancio@gmail.com> Wed Jun 06 17:08:48 2007 +0000
tree 9096b98d5bb87a5d8f34661e3e46e93328ca0433
parent 96dd9a8b1b969ece5504559ec240930bcb1dddd9

Fix PR1499.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37472 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Transforms/Scalar/InstructionCombining.cpp

diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index 2a22742..01fcfab 100644
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -1346,6 +1346,10 @@
       
       // Signed shift right.
       APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
+      // If any of the "high bits" are demanded, we should set the sign bit as
+      // demanded.
+      if (DemandedMask.countLeadingZeros() <= ShiftAmt)
+        DemandedMaskIn.set(BitWidth-1);
       if (SimplifyDemandedBits(I->getOperand(0),
                                DemandedMaskIn,
                                RHSKnownZero, RHSKnownOne, Depth+1))