| Analysing live variables ... |
| For BB 0x4d6510(L1Done) : |
| Defs: |
| In: 0x4d6398(i4) |
| Out: |
| For BB 0x5ab408(L1Header) : |
| Defs: 0x4c6528 0x4d6350(i3) 0x4d6398(i4) 0x4ddf50 0x5ab450(i2) |
| In: 0x4d8290(i1) 0x726c68(PhiCp:) |
| Out: |
| For BB 0x4d8248(Start) : |
| Defs: 0x4d8290(i1) 0x726c68(PhiCp:) |
| In: 0x4e4690(j) 0x501658(i) |
| Out: |
| |
| After Backward Pass 0... |
| For BB L1Done: |
| In: 0x4d6398(i4) |
| Out: |
| For BB L1Header: |
| In: 0x4d8290(i1) 0x726c68(PhiCp:) |
| Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) |
| For BB Start: |
| In: 0x4e4690(j) 0x501658(i) |
| Out: 0x4d8290(i1) 0x726c68(PhiCp:) |
| |
| After Backward Pass 1... |
| For BB L1Done: |
| In: 0x4d6398(i4) |
| Out: |
| For BB L1Header: |
| In: 0x4d8290(i1) 0x726c68(PhiCp:) |
| Out: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) |
| For BB Start: |
| In: 0x4e4690(j) 0x501658(i) |
| Out: 0x4d8290(i1) 0x726c68(PhiCp:) |
| Live Variable Analysis complete! |
| |
| ======For BB Start: Live var sets for instructions====== |
| |
| Live var sets before/after instruction nop |
| Before: 0x4d8290(i1) 0x726c68(PhiCp:) |
| After : 0x4d8290(i1) 0x726c68(PhiCp:) |
| |
| Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header) |
| Before: 0x4d8290(i1) 0x726c68(PhiCp:) |
| After : 0x4d8290(i1) 0x726c68(PhiCp:) |
| |
| Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val PhiCp:)* |
| Before: 0x4d8290(i1) |
| After : 0x4d8290(i1) 0x726c68(PhiCp:) |
| |
| Live var sets before/after instruction add %reg(val i) %reg(val j) %reg(val i1)* |
| Before: 0x4e4690(j) 0x501658(i) |
| After : 0x4d8290(i1) |
| |
| ======For BB L1Header: Live var sets for instructions====== |
| |
| Live var sets before/after instruction nop |
| Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) |
| After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) |
| |
| Live var sets before/after instruction ba %ccreg(val 0x0) %disp(label L1Header) |
| Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) |
| After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) |
| |
| Live var sets before/after instruction nop |
| Before: 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) |
| After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) |
| |
| Live var sets before/after instruction bg %ccreg(val 0x4ddf50) %disp(label L1Done) |
| Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:) |
| After : 0x4d6398(i4) 0x4d8290(i1) 0x726c68(PhiCp:) |
| |
| Live var sets before/after instruction add %reg(val i4) %reg(23) %reg(val PhiCp:)* |
| Before: 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 |
| After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 0x726c68(PhiCp:) |
| |
| Live var sets before/after instruction subcc %reg(val i4) %reg(val 0x4c6528) %reg(23)* %ccreg(val 0x4ddf50)* |
| Before: 0x4c6528 0x4d6398(i4) 0x4d8290(i1) |
| After : 0x4d6398(i4) 0x4d8290(i1) 0x4ddf50 |
| |
| Live var sets before/after instruction setsw 10 %reg(val 0x4c6528)* |
| Before: 0x4d6398(i4) 0x4d8290(i1) |
| After : 0x4c6528 0x4d6398(i4) 0x4d8290(i1) |
| |
| Live var sets before/after instruction add %reg(val i2) %reg(val i3) %reg(val i4)* |
| Before: 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2) |
| After : 0x4d6398(i4) 0x4d8290(i1) |
| |
| Live var sets before/after instruction add %reg(val i1) %reg(23) %reg(val i3)* |
| Before: 0x4d8290(i1) 0x5ab450(i2) |
| After : 0x4d6350(i3) 0x4d8290(i1) 0x5ab450(i2) |
| |
| Live var sets before/after instruction add %reg(val PhiCp:) %reg(23) %reg(val i2)* |
| Before: 0x4d8290(i1) 0x726c68(PhiCp:) |
| After : 0x4d8290(i1) 0x5ab450(i2) |
| |
| ======For BB L1Done: Live var sets for instructions====== |
| |
| Live var sets before/after instruction nop |
| Before: |
| After : |
| |
| Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x4d6398 |
| Before: 0x4d6398(i4) |
| After : |
| Analysing live variables ... |
| For BB 0x5ab498(bb0) : |
| Defs: 0x4daa90 0x4f2d68 0x4f2df8 0x501768(result) |
| In: |
| Out: |
| |
| After Backward Pass 0... |
| For BB bb0: |
| In: |
| Out: |
| Live Variable Analysis complete! |
| |
| ======For BB bb0: Live var sets for instructions====== |
| |
| Live var sets before/after instruction nop |
| Before: |
| After : |
| |
| Live var sets before/after instruction jmpl %reg(22)* 8 %reg(23) Implicit:0x501768 |
| Before: 0x501768(result) |
| After : |
| |
| Live var sets before/after instruction nop |
| Before: 0x501768(result) |
| After : 0x501768(result) |
| |
| Live var sets before/after instruction call %disp(label PhiTest) Implicit:0x4f2d68 0x4f2df8 0x501768* 0x4daa90* |
| Before: 0x4f2d68 0x4f2df8 |
| After : 0x501768(result) |
| |
| Live var sets before/after instruction setsw 17 %reg(val 0x4f2df8)* |
| Before: 0x4f2d68 |
| After : 0x4f2d68 0x4f2df8 |
| |
| Live var sets before/after instruction setsw 9 %reg(val 0x4f2d68)* |
| Before: |
| After : 0x4f2d68 |