Don't cache the TLI object since we have access to it through TargetMachine already.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184346 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
index 86e188a..2fb7664 100644
--- a/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
+++ b/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
@@ -55,15 +55,12 @@
return false;
}
-FunctionLoweringInfo::FunctionLoweringInfo(const TargetMachine &TM)
- : TM(TM), TLI(0) {
-}
-
void FunctionLoweringInfo::set(const Function &fn, MachineFunction &mf) {
+ const TargetLowering *TLI = TM.getTargetLowering();
+
Fn = &fn;
MF = &mf;
RegInfo = &MF->getRegInfo();
- TLI = TM.getTargetLowering();
// Check whether the function can return without sret-demotion.
SmallVector<ISD::OutputArg, 4> Outs;
@@ -209,7 +206,8 @@
/// CreateReg - Allocate a single virtual register for the given type.
unsigned FunctionLoweringInfo::CreateReg(MVT VT) {
- return RegInfo->createVirtualRegister(TLI->getRegClassFor(VT));
+ return RegInfo->
+ createVirtualRegister(TM.getTargetLowering()->getRegClassFor(VT));
}
/// CreateRegs - Allocate the appropriate number of virtual registers of
@@ -220,6 +218,8 @@
/// will assign registers for each member or element.
///
unsigned FunctionLoweringInfo::CreateRegs(Type *Ty) {
+ const TargetLowering *TLI = TM.getTargetLowering();
+
SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(*TLI, Ty, ValueVTs);
@@ -267,6 +267,8 @@
if (!Ty->isIntegerTy() || Ty->isVectorTy())
return;
+ const TargetLowering *TLI = TM.getTargetLowering();
+
SmallVector<EVT, 1> ValueVTs;
ComputeValueVTs(*TLI, Ty, ValueVTs);
assert(ValueVTs.size() == 1 &&