commit d67641b6f804110505a69aaed5479f446bbbb34e
author Jim Grosbach <grosbach@apple.com> Mon Dec 06 18:21:12 2010 +0000
committer Jim Grosbach <grosbach@apple.com> Mon Dec 06 18:21:12 2010 +0000
tree 9baa404393ea3272633276ac5e102a9ab57d772e
parent 9267d140dead8feec68f8503076fb9c743cce0f1

The ARM AsmMatcher needs to know that the CCOut operand is a register value,
not an immediate. It stores either ARM::CPSR or reg0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121018 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 12d892a..c0d2820 100644
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -103,6 +103,7 @@
 class ARMOperand : public MCParsedAsmOperand {
   enum KindTy {
     CondCode,
+    CCOut,
     Immediate,
     Memory,
     Register,
@@ -162,6 +163,7 @@
     case Token:
       Tok = o.Tok;
       break;
+    case CCOut:
     case Register:
       Reg = o.Reg;
       break;
@@ -195,7 +197,7 @@
   }
 
   unsigned getReg() const {
-    assert(Kind == Register && "Invalid access!");
+    assert(Kind == Register || Kind == CCOut && "Invalid access!");
     return Reg.RegNum;
   }
 
@@ -211,6 +213,7 @@
   }
 
   bool isCondCode() const { return Kind == CondCode; }
+  bool isCCOut() const { return Kind == CCOut; }
   bool isImm() const { return Kind == Immediate; }
   bool isReg() const { return Kind == Register; }
   bool isRegList() const { return Kind == RegisterList; }
@@ -264,6 +267,11 @@
     Inst.addOperand(MCOperand::CreateReg(0));
   }
 
+  void addCCOutOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::CreateReg(getReg()));
+  }
+
   void addRegOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::CreateReg(getReg()));
@@ -341,6 +349,14 @@
     return Op;
   }
 
+  static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
+    ARMOperand *Op = new ARMOperand(CCOut);
+    Op->Reg.RegNum = RegNum;
+    Op->StartLoc = S;
+    Op->EndLoc = S;
+    return Op;
+  }
+
   static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
     ARMOperand *Op = new ARMOperand(Token);
     Op->Tok.Data = Str.data();
@@ -418,6 +434,9 @@
   case CondCode:
     OS << ARMCondCodeToString(getCondCode());
     break;
+  case CCOut:
+    OS << "<ccout " << getReg() << ">";
+    break;
   case Immediate:
     getImm()->print(OS);
     break;