Add missing scheduling itineraries for transfers between core registers and VFP registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116983 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll
index 103ce33..19359a1 100644
--- a/test/CodeGen/ARM/fmscs.ll
+++ b/test/CodeGen/ARM/fmscs.ll
@@ -19,6 +19,6 @@
; NFP0: vnmls.f32 s2, s1, s0
; CORTEXA8: test:
-; CORTEXA8: vnmls.f32 s2, s1, s0
+; CORTEXA8: vnmls.f32 s1, s2, s0
; CORTEXA9: test:
; CORTEXA9: vnmls.f32 s0, s1, s2
diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll
index 1a95897..3909554 100644
--- a/test/CodeGen/ARM/reg_sequence.ll
+++ b/test/CodeGen/ARM/reg_sequence.ll
@@ -75,7 +75,8 @@
; CHECK: t3:
; CHECK: vld3.8
; CHECK: vmul.i8
-; CHECK-NOT: vmov
+; CHECK: vmov r
+; CHECK-NOT: vmov d
; CHECK: vst3.8
%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 1) ; <%struct.__neon_int8x8x3_t> [#uses=2]
%tmp2 = extractvalue %struct.__neon_int8x8x3_t %tmp1, 0 ; <<8 x i8>> [#uses=1]