commit d735b8019b0f297d7c14b55adcd887af24d8e602
author Dan Gohman <gohman@apple.com> Fri Oct 03 15:45:36 2008 +0000
committer Dan Gohman <gohman@apple.com> Fri Oct 03 15:45:36 2008 +0000
tree 9019ef6d07a30709c5afbe52903a7cdfd9615cb1
parent 06a62886fbca6214945958e28b16a82b470f6b2e

Switch the MachineOperand accessors back to the short names like
isReg, etc., from isRegister, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/SPUAsmPrinter.cpp

diff --git a/lib/Target/CellSPU/SPUAsmPrinter.cpp b/lib/Target/CellSPU/SPUAsmPrinter.cpp
index 8d9e891..c43ca0d 100644
--- a/lib/Target/CellSPU/SPUAsmPrinter.cpp
+++ b/lib/Target/CellSPU/SPUAsmPrinter.cpp
@@ -81,10 +81,10 @@
 
     void printOperand(const MachineInstr *MI, unsigned OpNo) {
       const MachineOperand &MO = MI->getOperand(OpNo);
-      if (MO.isRegister()) {
+      if (MO.isReg()) {
         assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
         O << TM.getRegisterInfo()->get(MO.getReg()).AsmName;
-      } else if (MO.isImmediate()) {
+      } else if (MO.isImm()) {
         O << MO.getImm();
       } else {
         printOp(MO);
@@ -186,8 +186,8 @@
     printMemRegImmS10(const MachineInstr *MI, unsigned OpNo)
     {
       const MachineOperand &MO = MI->getOperand(OpNo);
-      assert(MO.isImmediate()
-             && "printMemRegImmS10 first operand is not immedate");
+      assert(MO.isImm() &&
+             "printMemRegImmS10 first operand is not immedate");
       printS10ImmOperand(MI, OpNo);
       O << "(";
       printOperand(MI, OpNo+1);
@@ -198,11 +198,11 @@
     printAddr256K(const MachineInstr *MI, unsigned OpNo)
     {
       /* Note: operand 1 is an offset or symbol name. */
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         printS16ImmOperand(MI, OpNo);
       } else {
         printOp(MI->getOperand(OpNo));
-        if (MI->getOperand(OpNo+1).isImmediate()) {
+        if (MI->getOperand(OpNo+1).isImm()) {
           int displ = int(MI->getOperand(OpNo+1).getImm());
           if (displ > 0)
             O << "+" << displ;
@@ -222,7 +222,7 @@
     }
 
     void printSymbolHi(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         printS16ImmOperand(MI, OpNo);
       } else {
         printOp(MI->getOperand(OpNo));
@@ -231,7 +231,7 @@
     }
 
     void printSymbolLo(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         printS16ImmOperand(MI, OpNo);
       } else {
         printOp(MI->getOperand(OpNo));
@@ -245,7 +245,7 @@
     }
 
     void printROTHNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         int value = (int) MI->getOperand(OpNo).getImm();
         assert((value >= 0 && value < 16)
                && "Invalid negated immediate rotate 7-bit argument");
@@ -256,7 +256,7 @@
     }
 
     void printROTNeg7Imm(const MachineInstr *MI, unsigned OpNo) {
-      if (MI->getOperand(OpNo).isImmediate()) {
+      if (MI->getOperand(OpNo).isImm()) {
         int value = (int) MI->getOperand(OpNo).getImm();
         assert((value >= 0 && value < 32)
                && "Invalid negated immediate rotate 7-bit argument");
@@ -372,9 +372,9 @@
     default: return true;  // Unknown modifier.
     case 'L': // Write second word of DImode reference.  
       // Verify that this operand has two consecutive registers.
-      if (!MI->getOperand(OpNo).isRegister() ||
+      if (!MI->getOperand(OpNo).isReg() ||
           OpNo+1 == MI->getNumOperands() ||
-          !MI->getOperand(OpNo+1).isRegister())
+          !MI->getOperand(OpNo+1).isReg())
         return true;
       ++OpNo;   // Return the high-part.
       break;