| commit | db3bc87b16dd5dc1298870c05ae609f3b3272707 | [log] [tgz] |
|---|---|---|
| author | Anton Korobeynikov <asl@math.spbu.ru> | Thu Jul 16 14:10:17 2009 +0000 |
| committer | Anton Korobeynikov <asl@math.spbu.ru> | Thu Jul 16 14:10:17 2009 +0000 |
| tree | 20d9cddfb8a465fdfdb97ecbf75fd980ca20bdf4 | |
| parent | 9a05d96870061e5b5380cbec0c62ce00066e916f [diff] [blame] |
Consolidate reg-imm / reg-reg-imm address mode selection logic in one place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75990 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index 82018e8..c82aa0b 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -351,6 +351,9 @@ case SystemZ::MOV64m32r: Opc = SystemZ::MOV64m32ry; break; + case SystemZ::MOV8mi: + Opc = SystemZ::MOV8miy; + break; case SystemZ::MUL32rm: Opc = SystemZ::MUL32rmy; break;