Re-commit of the r48822, where the infinite looping problem discovered
by Dan Gohman is fixed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49330 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 4d4c929..00b5677 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -137,11 +137,11 @@
bool HasFlagUse = false;
for (SDNode::use_iterator UI = N->use_begin(), E = N->use_end();
UI != E; ++UI)
- if (FlagVal.isOperandOf(*UI)) {
+ if (FlagVal.isOperandOf(UI->getUser())) {
HasFlagUse = true;
NodeSUnit->FlaggedNodes.push_back(N);
SUnitMap[N].push_back(NodeSUnit);
- N = *UI;
+ N = UI->getUser();
break;
}
if (!HasFlagUse) break;
@@ -400,7 +400,7 @@
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
unsigned InstanceNo, unsigned SrcReg,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDOperandImpl, unsigned> &VRBaseMap) {
unsigned VRBase = 0;
if (TargetRegisterInfo::isVirtualRegister(SrcReg)) {
// Just use the input register directly!
@@ -416,7 +416,7 @@
bool MatchReg = true;
for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
UI != E; ++UI) {
- SDNode *Use = *UI;
+ SDNode *Use = UI->getUser();
bool Match = true;
if (Use->getOpcode() == ISD::CopyToReg &&
Use->getOperand(2).Val == Node &&
@@ -475,7 +475,7 @@
if (!Node->hasOneUse())
return 0;
- SDNode *Use = *Node->use_begin();
+ SDNode *Use = Node->use_begin()->getUser();
if (Use->getOpcode() == ISD::CopyToReg &&
Use->getOperand(2).Val == Node &&
Use->getOperand(2).ResNo == ResNo) {
@@ -488,7 +488,7 @@
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
const TargetInstrDesc &II,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDOperandImpl, unsigned> &VRBaseMap) {
assert(Node->getTargetOpcode() != TargetInstrInfo::IMPLICIT_DEF &&
"IMPLICIT_DEF should have been handled as a special case elsewhere!");
@@ -499,7 +499,7 @@
unsigned VRBase = 0;
for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
UI != E; ++UI) {
- SDNode *Use = *UI;
+ SDNode *Use = UI->getUser();
if (Use->getOpcode() == ISD::CopyToReg &&
Use->getOperand(2).Val == Node &&
Use->getOperand(2).ResNo == i) {
@@ -529,7 +529,7 @@
/// getVR - Return the virtual register corresponding to the specified result
/// of the specified node.
unsigned ScheduleDAG::getVR(SDOperand Op,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDOperandImpl, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode() &&
Op.getTargetOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
// Add an IMPLICIT_DEF instruction before every use.
@@ -544,7 +544,7 @@
return VReg;
}
- DenseMap<SDOperand, unsigned>::iterator I = VRBaseMap.find(Op);
+ DenseMap<SDOperandImpl, unsigned>::iterator I = VRBaseMap.find(Op);
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
return I->second;
}
@@ -557,7 +557,7 @@
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
const TargetInstrDesc *II,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDOperandImpl, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// include it because it is the most common and it makes the logic
@@ -688,7 +688,7 @@
/// EmitSubregNode - Generate machine code for subreg nodes.
///
void ScheduleDAG::EmitSubregNode(SDNode *Node,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDOperandImpl, unsigned> &VRBaseMap) {
unsigned VRBase = 0;
unsigned Opc = Node->getTargetOpcode();
@@ -696,7 +696,7 @@
// the CopyToReg'd destination register instead of creating a new vreg.
for (SDNode::use_iterator UI = Node->use_begin(), E = Node->use_end();
UI != E; ++UI) {
- SDNode *Use = *UI;
+ SDNode *Use = UI->getUser();
if (Use->getOpcode() == ISD::CopyToReg &&
Use->getOperand(2).Val == Node) {
unsigned DestReg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
@@ -779,7 +779,7 @@
/// EmitNode - Generate machine code for an node and needed dependencies.
///
void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
- DenseMap<SDOperand, unsigned> &VRBaseMap) {
+ DenseMap<SDOperandImpl, unsigned> &VRBaseMap) {
// If machine instruction
if (Node->isTargetOpcode()) {
unsigned Opc = Node->getTargetOpcode();
@@ -1099,7 +1099,7 @@
}
// Finally, emit the code for all of the scheduled instructions.
- DenseMap<SDOperand, unsigned> VRBaseMap;
+ DenseMap<SDOperandImpl, unsigned> VRBaseMap;
DenseMap<SUnit*, unsigned> CopyVRBaseMap;
for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
SUnit *SU = Sequence[i];