Add support for ARM halfword load/stores and signed byte loads with negative
offsets.
rdar://10412592
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144518 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index d330367..432abb5 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -875,8 +875,7 @@
needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset);
else
// ARM halfword load/stores and signed byte loads use +/-imm8 offsets.
- // FIXME: Negative offsets require special handling.
- needsLowering = (Addr.Offset > 255 || Addr.Offset < 0);
+ needsLowering = (Addr.Offset > 255 || Addr.Offset < -255);
break;
case MVT::f32:
case MVT::f64:
@@ -933,18 +932,26 @@
MIB.addFrameIndex(FI);
// ARM halfword load/stores and signed byte loads need an additional operand.
- if (useAM3) MIB.addReg(0);
-
- MIB.addImm(Addr.Offset);
+ if (useAM3) {
+ signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
+ MIB.addReg(0);
+ MIB.addImm(Imm);
+ } else {
+ MIB.addImm(Addr.Offset);
+ }
MIB.addMemOperand(MMO);
} else {
// Now add the rest of the operands.
MIB.addReg(Addr.Base.Reg);
// ARM halfword load/stores and signed byte loads need an additional operand.
- if (useAM3) MIB.addReg(0);
-
- MIB.addImm(Addr.Offset);
+ if (useAM3) {
+ signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset;
+ MIB.addReg(0);
+ MIB.addImm(Imm);
+ } else {
+ MIB.addImm(Addr.Offset);
+ }
}
AddOptionalDefs(MIB);
}