Tighten operand checking of register-shifted-register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index e7a6b89..0cbb765 100644
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -439,7 +439,7 @@
let PrintMethod = "printSORegRegOperand";
let DecoderMethod = "DecodeSORegRegOperand";
let ParserMatchClass = ShiftedRegAsmOperand;
- let MIOperandInfo = (ops GPR, GPR, i32imm);
+ let MIOperandInfo = (ops GPRnopc, GPRnopc, i32imm);
}
def ShiftedImmAsmOperand : AsmOperandClass { let Name = "RegShiftedImm"; }
@@ -2541,9 +2541,9 @@
let Inst{15-12} = Rd;
}
-def MOVsr : AsI1<0b1101, (outs GPR:$Rd), (ins shift_so_reg_reg:$src),
+def MOVsr : AsI1<0b1101, (outs GPRnopc:$Rd), (ins shift_so_reg_reg:$src),
DPSoRegRegFrm, IIC_iMOVsr,
- "mov", "\t$Rd, $src", [(set GPR:$Rd, shift_so_reg_reg:$src)]>,
+ "mov", "\t$Rd, $src", [(set GPRnopc:$Rd, shift_so_reg_reg:$src)]>,
UnaryDP {
bits<4> Rd;
bits<12> src;
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 4e7e582..59bed8d 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -683,8 +683,8 @@
unsigned Rs = fieldFromInstruction32(Val, 8, 4);
// Register-register
- DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
- DecodeGPRRegisterClass(Inst, Rs, Address, Decoder);
+ if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
+ if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false;
ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
switch (type) {