Tighten operand checking of register-shifted-register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137180 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 4e7e582..59bed8d 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -683,8 +683,8 @@
unsigned Rs = fieldFromInstruction32(Val, 8, 4);
// Register-register
- DecodeGPRRegisterClass(Inst, Rm, Address, Decoder);
- DecodeGPRRegisterClass(Inst, Rs, Address, Decoder);
+ if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
+ if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false;
ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
switch (type) {