commit e18cc42f7fa71407639499ec94eac259bd472bb3
author Evan Cheng <evan.cheng@apple.com> Mon Jan 19 19:06:11 2009 +0000
committer Evan Cheng <evan.cheng@apple.com> Mon Jan 19 19:06:11 2009 +0000
tree 6d5fa0e75ac8a8732c078504ae8cc185c32e2842
parent a7482db176741cf6d96d7905857f72bb9cf3437e

DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62519 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelDAGToDAG.cpp

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 842bb13..9b42d00 100644
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -1405,7 +1405,7 @@
         InFlag =
           CurDAG->getCopyToReg(CurDAG->getEntryNode(),
                                LoReg, N0, SDValue()).getValue(1);
-        if (isSigned) {
+        if (isSigned && !CurDAG->SignBitIsZero(N0)) {
           // Sign extend the low part into the high part.
           InFlag =
             SDValue(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);