- Expand tabs to spaces.
- select_bits.ll now fully functional now that PR1993 is closed. It was
previously broken by refactoring in SPUInstrInfo.td and using multiclasses.
- Same for eqv.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47972 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll
index 6858dba..46396eb 100644
--- a/test/CodeGen/CellSPU/and_ops.ll
+++ b/test/CodeGen/CellSPU/and_ops.ll
@@ -4,6 +4,7 @@
; RUN: grep andi %t1.s | count 36
; RUN: grep andhi %t1.s | count 30
; RUN: grep andbi %t1.s | count 4
+
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"
@@ -39,33 +40,33 @@
}
define i32 @and_i32_1(i32 %arg1, i32 %arg2) {
- %A = and i32 %arg2, %arg1
- ret i32 %A
+ %A = and i32 %arg2, %arg1
+ ret i32 %A
}
define i32 @and_i32_2(i32 %arg1, i32 %arg2) {
- %A = and i32 %arg1, %arg2
- ret i32 %A
+ %A = and i32 %arg1, %arg2
+ ret i32 %A
}
define i16 @and_i16_1(i16 %arg1, i16 %arg2) {
- %A = and i16 %arg2, %arg1
- ret i16 %A
+ %A = and i16 %arg2, %arg1
+ ret i16 %A
}
define i16 @and_i16_2(i16 %arg1, i16 %arg2) {
- %A = and i16 %arg1, %arg2
- ret i16 %A
+ %A = and i16 %arg1, %arg2
+ ret i16 %A
}
define i8 @and_i8_1(i8 %arg1, i8 %arg2) {
- %A = and i8 %arg2, %arg1
- ret i8 %A
+ %A = and i8 %arg2, %arg1
+ ret i8 %A
}
define i8 @and_i8_2(i8 %arg1, i8 %arg2) {
- %A = and i8 %arg1, %arg2
- ret i8 %A
+ %A = and i8 %arg1, %arg2
+ ret i8 %A
}
; ANDC instruction generation:
@@ -126,57 +127,57 @@
}
define i32 @andc_i32_1(i32 %arg1, i32 %arg2) {
- %A = xor i32 %arg2, -1
- %B = and i32 %A, %arg1
- ret i32 %B
+ %A = xor i32 %arg2, -1
+ %B = and i32 %A, %arg1
+ ret i32 %B
}
define i32 @andc_i32_2(i32 %arg1, i32 %arg2) {
- %A = xor i32 %arg1, -1
- %B = and i32 %A, %arg2
- ret i32 %B
+ %A = xor i32 %arg1, -1
+ %B = and i32 %A, %arg2
+ ret i32 %B
}
define i32 @andc_i32_3(i32 %arg1, i32 %arg2) {
- %A = xor i32 %arg2, -1
- %B = and i32 %arg1, %A
- ret i32 %B
+ %A = xor i32 %arg2, -1
+ %B = and i32 %arg1, %A
+ ret i32 %B
}
define i16 @andc_i16_1(i16 %arg1, i16 %arg2) {
- %A = xor i16 %arg2, -1
- %B = and i16 %A, %arg1
- ret i16 %B
+ %A = xor i16 %arg2, -1
+ %B = and i16 %A, %arg1
+ ret i16 %B
}
define i16 @andc_i16_2(i16 %arg1, i16 %arg2) {
- %A = xor i16 %arg1, -1
- %B = and i16 %A, %arg2
- ret i16 %B
+ %A = xor i16 %arg1, -1
+ %B = and i16 %A, %arg2
+ ret i16 %B
}
define i16 @andc_i16_3(i16 %arg1, i16 %arg2) {
- %A = xor i16 %arg2, -1
- %B = and i16 %arg1, %A
- ret i16 %B
+ %A = xor i16 %arg2, -1
+ %B = and i16 %arg1, %A
+ ret i16 %B
}
define i8 @andc_i8_1(i8 %arg1, i8 %arg2) {
- %A = xor i8 %arg2, -1
- %B = and i8 %A, %arg1
- ret i8 %B
+ %A = xor i8 %arg2, -1
+ %B = and i8 %A, %arg1
+ ret i8 %B
}
define i8 @andc_i8_2(i8 %arg1, i8 %arg2) {
- %A = xor i8 %arg1, -1
- %B = and i8 %A, %arg2
- ret i8 %B
+ %A = xor i8 %arg1, -1
+ %B = and i8 %A, %arg2
+ ret i8 %B
}
define i8 @andc_i8_3(i8 %arg1, i8 %arg2) {
- %A = xor i8 %arg2, -1
- %B = and i8 %arg1, %A
- ret i8 %B
+ %A = xor i8 %arg2, -1
+ %B = and i8 %arg1, %A
+ ret i8 %B
}
; ANDI instruction generation (i32 data type):
@@ -252,7 +253,7 @@
; i8 data type (s/b ANDBI if 8-bit registers were supported):
define <16 x i8> @and_v16i8(<16 x i8> %in) {
- ; ANDBI generated for vector types
+ ; ANDBI generated for vector types
%tmp2 = and <16 x i8> %in, < i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
i8 42, i8 42, i8 42, i8 42, i8 42, i8 42,
i8 42, i8 42, i8 42, i8 42 >
@@ -260,19 +261,19 @@
}
define i8 @and_u8(i8 zeroext %in) zeroext {
- ; ANDBI generated:
+ ; ANDBI generated:
%tmp37 = and i8 %in, 37
ret i8 %tmp37
}
define i8 @and_sext8(i8 signext %in) signext {
- ; ANDBI generated
+ ; ANDBI generated
%tmp38 = and i8 %in, 37
ret i8 %tmp38
}
define i8 @and_i8(i8 %in) {
- ; ANDBI generated
+ ; ANDBI generated
%tmp38 = and i8 %in, 205
ret i8 %tmp38
}