Register list operands are not allowed to contain only a single register. Alternate encodings are used in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143552 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 6927d2d..8dab153 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -1111,7 +1111,11 @@
}
// Empty register lists are not allowed.
- if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
+ uint32_t popcnt = CountPopulation_32(Val);
+ if (popcnt == 0) return MCDisassembler::Fail;
+ // and one-register lists are unpredictable.
+ else if (popcnt == 1) Check(S, MCDisassembler::SoftFail);
+
for (unsigned i = 0; i < 16; ++i) {
if (Val & (1 << i)) {
if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))