commit e3a7f7a2b20ad791626f58e16d76a514ea66b62b
author Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 14:14:54 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Thu Jul 16 14:14:54 2009 +0000
tree c49050e22582d5f8ac63553739654c29798a74a4
parent 0a42d2b4376526dbef25834b29a39fa684f9a902

Remove redundand register move

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76004 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
index 3df814e..c633766 100644
--- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -645,7 +645,7 @@
       default: assert(0 && "Unsupported VT!");
       case MVT::i32:
         Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m;
-        ClrOpc = SystemZ::MOV32ri16;
+        ClrOpc = SystemZ::MOV64Pr0_even;
         ResVT = MVT::v2i32;
         break;
       case MVT::i64:
@@ -669,15 +669,8 @@
                             CurDAG->getTargetConstant(subreg_odd, MVT::i32));
 
     // Zero out even subreg, if needed
-    if (ClrOpc) {
-      SDNode * ZeroHi = CurDAG->getTargetNode(SystemZ::MOV32ri16, dl, NVT,
-                                        CurDAG->getTargetConstant(0, MVT::i32));
-      Dividend =
-        CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
-                              SDValue(Dividend, 0),
-                              SDValue(ZeroHi, 0),
-                              CurDAG->getTargetConstant(subreg_even, MVT::i32));
-    }
+    if (ClrOpc)
+      Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
 
     SDNode *Result;
     SDValue DivVal = SDValue(Dividend, 0);
@@ -736,12 +729,12 @@
       default: assert(0 && "Unsupported VT!");
       case MVT::i32:
         Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m;
-        ClrOpc = SystemZ::MOV32ri16;
+        ClrOpc = SystemZ::MOV64Pr0_even;
         ResVT = MVT::v2i32;
         break;
       case MVT::i64:
         Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m;
-        ClrOpc = SystemZ::MOV64ri16;
+        ClrOpc = SystemZ::MOV128r0_even;
         ResVT = MVT::v2i64;
         break;
     }
@@ -760,15 +753,8 @@
                             SDValue(Tmp, 0), SDValue(Dividend, 0),
                             CurDAG->getTargetConstant(subreg_odd, MVT::i32));
 
-    // Zero out even subreg, if needed
-    SDNode * ZeroHi = CurDAG->getTargetNode(ClrOpc, dl, NVT,
-                                            CurDAG->getTargetConstant(0,
-                                                                      MVT::i32));
-    Dividend =
-      CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT,
-                            SDValue(Dividend, 0),
-                            SDValue(ZeroHi, 0),
-                            CurDAG->getTargetConstant(subreg_even, MVT::i32));
+    // Zero out even subreg
+    Dividend = CurDAG->getTargetNode(ClrOpc, dl, ResVT, SDValue(Dividend, 0));
 
     SDValue DivVal = SDValue(Dividend, 0);
     SDNode *Result;

lib/Target/SystemZ/SystemZInstrInfo.td

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
index 5a34d95..a1202aa 100644
--- a/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -370,6 +370,14 @@
                        "lmg\t{$from, $to, $dst}",
                        []>;
 
+let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
+def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
+                           "lhi\t${dst:subreg_even}, 0",
+                           []>;
+def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
+                           "lghi\t${dst:subreg_even}, 0",
+                           []>;
+}
 
 //===----------------------------------------------------------------------===//
 // Arithmetic Instructions