Allocate virtual registers in ascending order.
This is just the fallback tie-breaker ordering, the main allocation
order is still descending size.
Patch by Shamil Kurmangaleev!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153904 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll
index f1bd7ee..3e07da8 100644
--- a/test/CodeGen/ARM/select.ll
+++ b/test/CodeGen/ARM/select.ll
@@ -76,12 +76,12 @@
; block generated, odds are good that we have close to the ideal code for this:
;
; CHECK-NEON: _f8:
-; CHECK-NEON: adr r2, LCPI7_0
-; CHECK-NEON-NEXT: movw r3, #1123
-; CHECK-NEON-NEXT: adds r1, r2, #4
-; CHECK-NEON-NEXT: cmp r0, r3
+; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0
+; CHECK-NEON-NEXT: movw [[R3:r[0-9]+]], #1123
+; CHECK-NEON-NEXT: adds {{r.*}}, [[R2]], #4
+; CHECK-NEON-NEXT: cmp r0, [[R3]]
; CHECK-NEON-NEXT: it ne
-; CHECK-NEON-NEXT: movne r1, r2
+; CHECK-NEON-NEXT: movne {{r.*}}, [[R2]]
; CHECK-NEON-NEXT: ldr
; CHECK-NEON: bx