fix rdar://8431880 - rcl/rcr with no shift amount not recognized
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113936 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index 7098c58..4856cc9 100644
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -813,7 +813,7 @@
if (getLexer().is(AsmToken::EndOfStatement))
Parser.Lex(); // Consume the EndOfStatement
- // FIXME: Hack to handle recognize s{hr,ar,hl} <op>, $1. Canonicalize to
+ // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
// "shift <op>".
if ((Name.startswith("shr") || Name.startswith("sar") ||
Name.startswith("shl")) &&
@@ -825,6 +825,14 @@
Operands.erase(Operands.begin() + 1);
}
}
+
+ // FIXME: Hack to handle recognize "rc[lr] <op>" -> "rcl $1, <op>".
+ if ((Name.startswith("rcl") || Name.startswith("rcr")) &&
+ Operands.size() == 2) {
+ const MCExpr *One = MCConstantExpr::Create(1, getParser().getContext());
+ Operands.push_back(X86Operand::CreateImm(One, NameLoc, NameLoc));
+ std::swap(Operands[1], Operands[2]);
+ }
// FIXME: Hack to handle recognize "in[bwl] <op>". Canonicalize it to
// "inb <op>, %al".