more condition codes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30567 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 74bfdc3..8c9cf27 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -87,7 +87,14 @@
/// DAGCCToARMCC - Convert a DAG integer condition code to an ARM CC
static ARMCC::CondCodes DAGCCToARMCC(ISD::CondCode CC) {
switch (CC) {
- default: assert(0 && "Unknown condition code!");
+ default:
+ std::cerr << "CC = " << CC << "\n";
+ assert(0 && "Unknown condition code!");
+ case ISD::SETUGT: return ARMCC::HI;
+ case ISD::SETULE: return ARMCC::LS;
+ case ISD::SETLE: return ARMCC::LE;
+ case ISD::SETLT: return ARMCC::LT;
+ case ISD::SETGT: return ARMCC::GT;
case ISD::SETNE: return ARMCC::NE;
case ISD::SETEQ: return ARMCC::EQ;
case ISD::SETGE: return ARMCC::GE;