commit ede042dc8d59ff48a48ef8e2271f2a7ee8324ba5
author Owen Anderson <resistor@mac.com> Thu Sep 15 18:36:29 2011 +0000
committer Owen Anderson <resistor@mac.com> Thu Sep 15 18:36:29 2011 +0000
tree 1863d77a0f4430e093ef2933f38f299a5992c74b
parent 01afdb3a45f63af540b43b414c6094220a8f91e7

Add support for stored annotations to MCInst, and provide facilities for MC-based InstPrinters to print them out.  Enhance the ARM and X86 InstPrinter's to do so in verbose mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139820 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
index 7eec0dd..289d192 100644
--- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
+++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
@@ -71,6 +71,9 @@
 
     O << ", " << getRegisterName(MO2.getReg());
     assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
+
+    if (CommentStream) printAnnotations(MI, *CommentStream);
+
     return;
   }
 
@@ -87,10 +90,14 @@
     O << '\t' << getRegisterName(Dst.getReg())
       << ", " << getRegisterName(MO1.getReg());
 
-    if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx)
+    if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
+      if (CommentStream) printAnnotations(MI, *CommentStream);
       return;
+    }
 
     O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
+
+    if (CommentStream) printAnnotations(MI, *CommentStream);
     return;
   }
 
@@ -104,6 +111,7 @@
       O << ".w";
     O << '\t';
     printRegisterList(MI, 4, O);
+    if (CommentStream) printAnnotations(MI, *CommentStream);
     return;
   }
   if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
@@ -111,6 +119,7 @@
     O << '\t' << "push";
     printPredicateOperand(MI, 4, O);
     O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
+    if (CommentStream) printAnnotations(MI, *CommentStream);
     return;
   }
 
@@ -123,6 +132,7 @@
       O << ".w";
     O << '\t';
     printRegisterList(MI, 4, O);
+    if (CommentStream) printAnnotations(MI, *CommentStream);
     return;
   }
   if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
@@ -130,6 +140,7 @@
     O << '\t' << "pop";
     printPredicateOperand(MI, 5, O);
     O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
+    if (CommentStream) printAnnotations(MI, *CommentStream);
     return;
   }
 
@@ -141,6 +152,7 @@
     printPredicateOperand(MI, 2, O);
     O << '\t';
     printRegisterList(MI, 4, O);
+    if (CommentStream) printAnnotations(MI, *CommentStream);
     return;
   }
 
@@ -151,6 +163,7 @@
     printPredicateOperand(MI, 2, O);
     O << '\t';
     printRegisterList(MI, 4, O);
+    if (CommentStream) printAnnotations(MI, *CommentStream);
     return;
   }
 
@@ -169,6 +182,7 @@
     if (Writeback) O << "!";
     O << ", ";
     printRegisterList(MI, 3, O);
+    if (CommentStream) printAnnotations(MI, *CommentStream);
     return;
   }
 
@@ -177,10 +191,12 @@
       MI->getOperand(1).getReg() == ARM::R8) {
     O << "\tnop";
     printPredicateOperand(MI, 2, O);
+    if (CommentStream) printAnnotations(MI, *CommentStream);
     return;
   }
 
   printInstruction(MI, O);
+  if (CommentStream) printAnnotations(MI, *CommentStream);
 }
 
 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,