MachineLICM CSE should match destination register classes; avoid hoisting implicit_def's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65592 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/MachineLICM.cpp b/lib/CodeGen/MachineLICM.cpp
index dd32977..aaa4de4 100644
--- a/lib/CodeGen/MachineLICM.cpp
+++ b/lib/CodeGen/MachineLICM.cpp
@@ -288,6 +288,9 @@
/// IsProfitableToHoist - Return true if it is potentially profitable to hoist
/// the given loop invariant.
bool MachineLICM::IsProfitableToHoist(MachineInstr &MI) {
+ if (MI.getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
+ return false;
+
const TargetInstrDesc &TID = MI.getDesc();
// FIXME: For now, only hoist re-materilizable instructions. LICM will
@@ -312,7 +315,8 @@
}
static const MachineInstr *LookForDuplicate(const MachineInstr *MI,
- std::vector<const MachineInstr*> &PrevMIs) {
+ std::vector<const MachineInstr*> &PrevMIs,
+ MachineRegisterInfo *RegInfo) {
unsigned NumOps = MI->getNumOperands();
for (unsigned i = 0, e = PrevMIs.size(); i != e; ++i) {
const MachineInstr *PrevMI = PrevMIs[i];
@@ -322,8 +326,14 @@
bool IsSame = true;
for (unsigned j = 0; j != NumOps; ++j) {
const MachineOperand &MO = MI->getOperand(j);
- if (MO.isReg() && MO.isDef())
+ if (MO.isReg() && MO.isDef()) {
+ if (RegInfo->getRegClass(MO.getReg()) !=
+ RegInfo->getRegClass(PrevMI->getOperand(j).getReg())) {
+ IsSame = false;
+ break;
+ }
continue;
+ }
if (!MO.isIdenticalTo(PrevMI->getOperand(j))) {
IsSame = false;
break;
@@ -362,7 +372,7 @@
std::vector<const MachineInstr*> >::iterator CI = CSEMap.find(BBOpcPair);
bool DoneCSE = false;
if (CI != CSEMap.end()) {
- const MachineInstr *Dup = LookForDuplicate(&MI, CI->second);
+ const MachineInstr *Dup = LookForDuplicate(&MI, CI->second, RegInfo);
if (Dup) {
DOUT << "CSEing " << MI;
DOUT << " with " << *Dup;