Perform more thorough checking of t2IT mask parameters, which fixes all remaining crashers when disassembling the entire 16-bit instruction space.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138507 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index d7e92db..bb6b767 100644
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -20,6 +20,7 @@
// IT block condition mask
def it_mask : Operand<i32> {
let PrintMethod = "printThumbITMask";
+ let DecoderMethod = "DecodeITMask";
}
// Shifted operands. No register controlled shifts for Thumb2.
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index e221269..83a8f80 100644
--- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -230,6 +230,8 @@
uint64_t Address, const void *Decoder);
static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val,
+ uint64_t Address, const void *Decoder);
#include "ARMGenDisassemblerTables.inc"
#include "ARMGenInstrInfo.inc"
@@ -3304,3 +3306,14 @@
return S;
}
+static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask,
+ uint64_t Address, const void *Decoder) {
+ DecodeStatus S = Success;
+ if (Mask == 0) {
+ Mask = 0x8;
+ CHECK(S, Unpredictable);
+ }
+ Inst.addOperand(MCOperand::CreateImm(Mask));
+ return S;
+}
+