Make x86 test actually test x86 code generation. Fix the
construct on ARM, which was breaking by coincidence, and add a similar
testcase for ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79719 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/vshift_split.ll b/test/CodeGen/ARM/vshift_split.ll
new file mode 100644
index 0000000..a44db66
--- /dev/null
+++ b/test/CodeGen/ARM/vshift_split.ll
@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc -march=arm -mattr=-neon
+
+; Example that requires splitting and expanding a vector shift.
+define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
+entry:
+ %shr = lshr <2 x i64> %val, < i64 2, i64 2 > ; <<2 x i64>> [#uses=1]
+ ret <2 x i64> %shr
+}