Fix a TargetLowering optimization so that it doesn't duplicate
loads when an input node has multiple uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68398 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 3f0bf5b..79a48a6 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1464,6 +1464,7 @@
// in the same partial word, see if we can shorten the load.
if (DCI.isBeforeLegalize() &&
N0.getOpcode() == ISD::AND && C1 == 0 &&
+ N0.getNode()->hasOneUse() &&
isa<LoadSDNode>(N0.getOperand(0)) &&
N0.getOperand(0).getNode()->hasOneUse() &&
isa<ConstantSDNode>(N0.getOperand(1))) {
diff --git a/test/CodeGen/X86/and-su.ll b/test/CodeGen/X86/and-su.ll
new file mode 100644
index 0000000..bdc8454
--- /dev/null
+++ b/test/CodeGen/X86/and-su.ll
@@ -0,0 +1,16 @@
+; RUN: llvm-as < %s | llc -march=x86 | grep {(%} | count 1
+
+; Don't duplicate the load.
+
+define fastcc i32 @foo(i32* %p) nounwind {
+ %t0 = load i32* %p
+ %t2 = and i32 %t0, 10
+ %t3 = icmp ne i32 %t2, 0
+ br i1 %t3, label %bb63, label %bb76
+
+bb63:
+ ret i32 %t2
+
+bb76:
+ ret i32 0
+}