commit f5732c4ee5af93bddeb8f4612441bfdf19237ea3
author Eric Christopher <echristo@apple.com> Tue Sep 28 00:35:09 2010 +0000
committer Eric Christopher <echristo@apple.com> Tue Sep 28 00:35:09 2010 +0000
tree aa06a5cbf45b918c2b520562c30ea98e66f44094
parent ee70fa77b4f8bdfd93741609a4d33a831476d505

Fix fp constant loads to have a destination register.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114930 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMFastISel.cpp

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index e84989c..eb27fad 100644
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -397,8 +397,9 @@
   unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
   
   // The extra reg is for addrmode5.
-  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc))
-                  .addReg(DestReg).addConstantPoolIndex(Idx)
+  AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
+                          DestReg)
+                  .addConstantPoolIndex(Idx)
                   .addReg(0));
   return DestReg;
 }