Make getClass more robust by adding cLong.
Add handling for Mul instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12450 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SparcV8/InstSelectSimple.cpp b/lib/Target/SparcV8/InstSelectSimple.cpp
index 90fdacb..1ba4285 100644
--- a/lib/Target/SparcV8/InstSelectSimple.cpp
+++ b/lib/Target/SparcV8/InstSelectSimple.cpp
@@ -143,7 +143,7 @@
}
enum TypeClass {
- cByte, cShort, cInt, cFloat, cDouble
+ cByte, cShort, cInt, cLong, cFloat, cDouble
};
static TypeClass getClass (const Type *T) {
@@ -151,6 +151,7 @@
case Type::UByteTyID: case Type::SByteTyID: return cByte;
case Type::UShortTyID: case Type::ShortTyID: return cShort;
case Type::UIntTyID: case Type::IntTyID: return cInt;
+ case Type::ULongTyID: case Type::LongTyID: return cLong;
case Type::FloatTyID: return cFloat;
case Type::DoubleTyID: return cDouble;
default:
@@ -261,6 +262,11 @@
case Instruction::Sub:
BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
break;
+ case Instruction::Mul: {
+ unsigned MulOpcode = I.getType ()->isSigned () ? V8::SMULrr : V8::UMULrr;
+ BuildMI (BB, MulOpcode, 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
+ break;
+ }
default:
visitInstruction (I);
return;