commit f595266b91ea5aef953ce3019557a5f3d3291ff9
author Mon P Wang <wangmp@apple.com> Thu Jul 17 04:54:06 2008 +0000
committer Mon P Wang <wangmp@apple.com> Thu Jul 17 04:54:06 2008 +0000
tree 9c1503c9a16a588597cf266ad81f6f863dab0ef5
parent b2ff885aaed8f9b033b16ca78d645650efc32433

When lowering certain atomics, we need to copy the memoperand from the old
atomic operation to the new one.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53714 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 5620d92..1c93477 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -6010,7 +6010,9 @@
   for (int i=0; i <= lastAddrIndx; ++i)
     (*MIB).addOperand(*argOpers[i]);
   MIB.addReg(t2);
-  
+  assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
+  (*MIB).addMemOperand(*F, *bInstr->memoperands_begin());
+
   MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
   MIB.addReg(X86::EAX);
   
@@ -6107,6 +6109,8 @@
   for (int i=0; i <= lastAddrIndx; ++i)
     (*MIB).addOperand(*argOpers[i]);
   MIB.addReg(t3);
+  assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand");
+  (*MIB).addMemOperand(*F, *mInstr->memoperands_begin());
   
   MIB = BuildMI(newMBB, TII->get(X86::MOV32rr), destOper.getReg());
   MIB.addReg(X86::EAX);