commit f5da5900648985cf7c328eec684a0596a05c17fb
author Chris Lattner <sabre@nondot.org> Sat Jun 20 07:03:18 2009 +0000
committer Chris Lattner <sabre@nondot.org> Sat Jun 20 07:03:18 2009 +0000
tree 40b96f97a28a3ce6e9e2635ffebac6e4e627653e
parent b8fabe260483cfb16ea12b872c7f9fa2ffaf1433

implement support for lowering subregs when preparing to print 
LEA64_32r, eliminating a bunch of modifier logic stuff on addr modes.

Implement support for printing mbb labels as operands.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73817 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp

diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
index a34b675..059bb34 100644
--- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
@@ -762,6 +762,18 @@
   return false;
 }
 
+static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) {
+  // Convert registers in the addr mode according to subreg64.
+  for (unsigned i = 0; i != 4; ++i) {
+    if (!MI->getOperand(i).isReg()) continue;
+    
+    unsigned Reg = MI->getOperand(i).getReg();
+    if (Reg == 0) continue;
+    
+    MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, MVT::i64));
+  }
+}
+
 /// printMachineInstruction -- Print out a single X86 LLVM instruction MI in
 /// AT&T syntax to the current output stream.
 ///
@@ -769,6 +781,21 @@
   ++EmittedInsts;
 
   if (NewAsmPrinter) {
+    if (MI->getOpcode() == TargetInstrInfo::INLINEASM) {
+      O << "\t";
+      printInlineAsm(MI);
+      return;
+    } else if (MI->isLabel()) {
+      printLabel(MI);
+      return;
+    } else if (MI->getOpcode() == TargetInstrInfo::DECLARE) {
+      printDeclare(MI);
+      return;
+    } else if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF) {
+      printImplicitDef(MI);
+      return;
+    }
+    
     O << "NEW: ";
     MCInst TmpInst;
     
@@ -782,6 +809,8 @@
         MCOp.MakeReg(MO.getReg());
       } else if (MO.isImm()) {
         MCOp.MakeImm(MO.getImm());
+      } else if (MO.isMBB()) {
+        MCOp.MakeMBBLabel(getFunctionNumber(), MO.getMBB()->getNumber());
       } else {
         assert(0 && "Unimp");
       }
@@ -789,9 +818,9 @@
       TmpInst.addOperand(MCOp);
     }
     
-    if (MI->getOpcode() == X86::LEA64_32r) {
+    if (TmpInst.getOpcode() == X86::LEA64_32r) {
       // Should handle the 'subreg rewriting' for the lea64_32mem operand.
-      
+      lower_lea64_32mem(&TmpInst, 1);
     }
     
     // FIXME: Convert TmpInst.