Plugin new subtarget backend into the build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23870 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index baa15eb..d356e57 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -25,6 +25,7 @@
#include "AsmWriterEmitter.h"
#include "InstrSelectorEmitter.h"
#include "DAGISelEmitter.h"
+#include "SubtargetEmitter.h"
#include <algorithm>
#include <cstdio>
#include <fstream>
@@ -36,6 +37,7 @@
GenRegisterEnums, GenRegister, GenRegisterHeader,
GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector,
GenDAGISel,
+ GenSubtarget,
PrintEnums,
Parse
};
@@ -63,6 +65,8 @@
"Generate an instruction selector"),
clEnumValN(GenDAGISel, "gen-dag-isel",
"Generate a DAG instruction selector"),
+ clEnumValN(GenSubtarget, "gen-subtarget",
+ "Generate subtarget enumerations"),
clEnumValN(PrintEnums, "print-enums",
"Print enum values for a class"),
clEnumValN(Parse, "parse",
@@ -472,6 +476,9 @@
case GenDAGISel:
DAGISelEmitter(Records).run(*Out);
break;
+ case GenSubtarget:
+ SubtargetEmitter(Records).run(*Out);
+ break;
case PrintEnums:
{
std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);