diff --git a/include/llvm/CodeGen/DFAPacketizer.h b/include/llvm/CodeGen/DFAPacketizer.h
index 38a899f..933e6e0 100644
--- a/include/llvm/CodeGen/DFAPacketizer.h
+++ b/include/llvm/CodeGen/DFAPacketizer.h
@@ -42,35 +42,35 @@
   const int (*DFAStateInputTable)[2];
   const unsigned *DFAStateEntryTable;
 
-  // CachedTable is a map from <FromState, Input> to ToState
+  // CachedTable is a map from <FromState, Input> to ToState.
   DenseMap<UnsignPair, unsigned> CachedTable;
 
-  // ReadTable - Read the DFA transition table and update CachedTable
+  // ReadTable - Read the DFA transition table and update CachedTable.
   void ReadTable(unsigned int state);
 
 public:
   DFAPacketizer(const InstrItineraryData* I, const int (*SIT)[2],
                 const unsigned* SET);
 
-  // Reset the current state to make all resources available
+  // Reset the current state to make all resources available.
   void clearResources() {
     CurrentState = 0;
   }
 
   // canReserveResources - Check if the resources occupied by a MCInstrDesc
-  // are available in the current state
+  // are available in the current state.
   bool canReserveResources(const llvm::MCInstrDesc* MID);
 
   // reserveResources - Reserve the resources occupied by a MCInstrDesc and
-  // change the current state to reflect that change
+  // change the current state to reflect that change.
   void reserveResources(const llvm::MCInstrDesc* MID);
 
   // canReserveResources - Check if the resources occupied by a machine
-  // instruction are available in the current state
+  // instruction are available in the current state.
   bool canReserveResources(llvm::MachineInstr* MI);
 
   // reserveResources - Reserve the resources occupied by a machine
-  // instruction and change the current state to reflect that change
+  // instruction and change the current state to reflect that change.
   void reserveResources(llvm::MachineInstr* MI);
 };
 }
diff --git a/lib/CodeGen/DFAPacketizer.cpp b/lib/CodeGen/DFAPacketizer.cpp
index f80f160..c0e505f 100644
--- a/lib/CodeGen/DFAPacketizer.cpp
+++ b/lib/CodeGen/DFAPacketizer.cpp
@@ -35,7 +35,7 @@
 
 
 //
-// ReadTable - Read the DFA transition table and update CachedTable
+// ReadTable - Read the DFA transition table and update CachedTable.
 //
 // Format of the transition tables:
 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
@@ -47,7 +47,7 @@
   unsigned ThisState = DFAStateEntryTable[state];
   unsigned NextStateInTable = DFAStateEntryTable[state+1];
   // Early exit in case CachedTable has already contains this
-  // state's transitions
+  // state's transitions.
   if (CachedTable.count(UnsignPair(state,
                                    DFAStateInputTable[ThisState][0])))
     return;
@@ -59,7 +59,7 @@
 
 
 // canReserveResources - Check if the resources occupied by a MCInstrDesc
-// are available in the current state
+// are available in the current state.
 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc* MID) {
   unsigned InsnClass = MID->getSchedClass();
   const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass);
@@ -71,7 +71,7 @@
 
 
 // reserveResources - Reserve the resources occupied by a MCInstrDesc and
-// change the current state to reflect that change
+// change the current state to reflect that change.
 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc* MID) {
   unsigned InsnClass = MID->getSchedClass();
   const llvm::InstrStage* IS = InstrItins->beginStage(InsnClass);
@@ -84,14 +84,14 @@
 
 
 // canReserveResources - Check if the resources occupied by a machine
-// instruction are available in the current state
+// instruction are available in the current state.
 bool DFAPacketizer::canReserveResources(llvm::MachineInstr* MI) {
   const llvm::MCInstrDesc& MID = MI->getDesc();
   return canReserveResources(&MID);
 }
 
 // reserveResources - Reserve the resources occupied by a machine
-// instruction and change the current state to reflect that change
+// instruction and change the current state to reflect that change.
 void DFAPacketizer::reserveResources(llvm::MachineInstr* MI) {
   const llvm::MCInstrDesc& MID = MI->getDesc();
   reserveResources(&MID);
diff --git a/utils/TableGen/DFAPacketizerEmitter.cpp b/utils/TableGen/DFAPacketizerEmitter.cpp
index b5aeec6..32bb26e 100644
--- a/utils/TableGen/DFAPacketizerEmitter.cpp
+++ b/utils/TableGen/DFAPacketizerEmitter.cpp
@@ -29,19 +29,19 @@
 // State represents the usage of machine resources if the packet contains
 // a set of instruction classes.
 //
-// Specifically, currentState is a set of bit-masks
+// Specifically, currentState is a set of bit-masks.
 // The nth bit in a bit-mask indicates whether the nth resource is being used
 // by this state. The set of bit-masks in a state represent the different
 // possible outcomes of transitioning to this state.
-// For example: Consider a two resource architecture: Resource L and Resource M
-// with three instruction classes: L, M, and L_or_M
+// For example: consider a two resource architecture: resource L and resource M
+// with three instruction classes: L, M, and L_or_M.
 // From the initial state (currentState = 0x00), if we add instruction class
 // L_or_M we will transition to a state with currentState = [0x01, 0x10]. This
 // represents the possible resource states that can result from adding a L_or_M
 // instruction
 //
 // Another way of thinking about this transition is we are mapping a NDFA with
-// two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10]
+// two states [0x01] and [0x10] into a DFA with a single state [0x01, 0x10].
 //
 //
 namespace {
@@ -57,15 +57,15 @@
 
   //
   // canAddInsnClass - Returns true if an instruction of type InsnClass is a
-  // valid transition from this state i.e., can an instruction of type InsnClass
-  // be added to the packet represented by this state
+  // valid transition from this state, i.e., can an instruction of type InsnClass
+  // be added to the packet represented by this state.
   //
   // PossibleStates is the set of valid resource states that ensue from valid
-  // transitions
+  // transitions.
   //
   bool canAddInsnClass(unsigned InsnClass, std::set<unsigned>& PossibleStates);
 };
-} // End anonymous namespace
+} // End anonymous namespace.
 
 
 namespace {
@@ -79,39 +79,39 @@
 
   Transition(State* from_, unsigned input_, State* to_);
 };
-} // End anonymous namespace
+} // End anonymous namespace.
 
 
 //
-// Comparators to keep set of states sorted
+// Comparators to keep set of states sorted.
 //
 namespace {
 struct ltState {
   bool operator()(const State* s1, const State* s2) const;
 };
-} // End anonymous namespace
+} // End anonymous namespace.
 
 
 //
-// class DFA: deterministic finite automaton for processor resource tracking
+// class DFA: deterministic finite automaton for processor resource tracking.
 //
 namespace {
 class DFA {
 public:
   DFA();
 
-  // Set of states. Need to keep this sorted to emit the transition table
+  // Set of states. Need to keep this sorted to emit the transition table.
   std::set<State*, ltState> states;
 
-  // Map from a state to the list of transitions with that state as source
+  // Map from a state to the list of transitions with that state as source.
   std::map<State*, SmallVector<Transition*, 16>, ltState> stateTransitions;
   State* currentState;
 
-  // Highest valued Input seen
+  // Highest valued Input seen.
   unsigned LargestInput;
 
   //
-  // Modify the DFA
+  // Modify the DFA.
   //
   void initialize();
   void addState(State*);
@@ -119,22 +119,22 @@
 
   //
   // getTransition -  Return the state when a transition is made from
-  // State From with Input I. If a transition is not found, return NULL
+  // State From with Input I. If a transition is not found, return NULL.
   //
   State* getTransition(State*, unsigned);
 
   //
   // isValidTransition: Predicate that checks if there is a valid transition
-  // from state From on input InsnClass
+  // from state From on input InsnClass.
   //
   bool isValidTransition(State* From, unsigned InsnClass);
 
   //
-  // writeTable: Print out a table representing the DFA
+  // writeTable: Print out a table representing the DFA.
   //
   void writeTableAndAPI(raw_ostream &OS, const std::string& ClassName);
 };
-} // End anonymous namespace
+} // End anonymous namespace.
 
 
 //
@@ -166,15 +166,15 @@
 //
 // canAddInsnClass - Returns true if an instruction of type InsnClass is a
 // valid transition from this state i.e., can an instruction of type InsnClass
-// be added to the packet represented by this state
+// be added to the packet represented by this state.
 //
 // PossibleStates is the set of valid resource states that ensue from valid
-// transitions
+// transitions.
 //
 bool State::canAddInsnClass(unsigned InsnClass,
                             std::set<unsigned>& PossibleStates) {
   //
-  // Iterate over all resource states in currentState
+  // Iterate over all resource states in currentState.
   //
   bool AddedState = false;
 
@@ -183,8 +183,8 @@
     unsigned thisState = *SI;
 
     //
-    // Iterate over all possible resources used in InsnClass
-    // For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}
+    // Iterate over all possible resources used in InsnClass.
+    // For ex: for InsnClass = 0x11, all resources = {0x01, 0x10}.
     //
 
     DenseSet<unsigned> VisitedResourceStates;
@@ -192,18 +192,18 @@
       if ((0x1 << j) & InsnClass) {
         //
         // For each possible resource used in InsnClass, generate the
-        // resource state if that resource was used
+        // resource state if that resource was used.
         //
         unsigned ResultingResourceState = thisState | (0x1 << j);
         //
         // Check if the resulting resource state can be accommodated in this
-        // packet
-        // We compute ResultingResourceState OR thisState
+        // packet.
+        // We compute ResultingResourceState OR thisState.
         // If the result of the OR is different than thisState, it implies
         // that there is at least one resource that can be used to schedule
-        // InsnClass in the current packet
+        // InsnClass in the current packet.
         // Insert ResultingResourceState into PossibleStates only if we haven't
-        // processed ResultingResourceState before
+        // processed ResultingResourceState before.
         //
         if ((ResultingResourceState != thisState) &&
             (VisitedResourceStates.count(ResultingResourceState) == 0)) {
@@ -231,18 +231,18 @@
 
 
 void DFA::addTransition(Transition* T) {
-  // Update LargestInput
+  // Update LargestInput.
   if (T->input > LargestInput)
     LargestInput = T->input;
 
-  // Add the new transition
+  // Add the new transition.
   stateTransitions[T->from].push_back(T);
 }
 
 
 //
 // getTransition - Return the state when a transition is made from
-// State From with Input I. If a transition is not found, return NULL
+// State From with Input I. If a transition is not found, return NULL.
 //
 State* DFA::getTransition(State* From, unsigned I) {
   // Do we have a transition from state From?
@@ -275,26 +275,26 @@
 
 //
 // writeTableAndAPI - Print out a table representing the DFA and the
-// associated API to create a DFA packetizer
+// associated API to create a DFA packetizer.
 //
 // Format:
 // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid
-//                           transitions
+//                           transitions.
 // DFAStateEntryTable[i] = Index of the first entry in DFAStateInputTable for
-//                         the ith state
+//                         the ith state.
 //
 //
 void DFA::writeTableAndAPI(raw_ostream &OS, const std::string& TargetName) {
   std::set<State*, ltState>::iterator SI = states.begin();
   // This table provides a map to the beginning of the transitions for State s
-  // in DFAStateInputTable i.e.,
+  // in DFAStateInputTable.
   std::vector<int> StateEntry(states.size());
 
   OS << "namespace llvm {\n\n";
   OS << "const int " << TargetName << "DFAStateInputTable[][2] = {\n";
 
   // Tracks the total valid transitions encountered so far. It is used
-  // to construct the StateEntry table
+  // to construct the StateEntry table.
   int ValidTransitions = 0;
   for (unsigned i = 0; i < states.size(); ++i, ++SI) {
     StateEntry[i] = ValidTransitions;
@@ -309,8 +309,8 @@
       ++ValidTransitions;
     }
 
-    /* If there are no valid transitions from this stage, we need a sentinel
-       transition */
+    // If there are no valid transitions from this stage, we need a sentinel
+    // transition.
     if (ValidTransitions == StateEntry[i])
       OS << "{-1, -1},";
 
@@ -320,7 +320,7 @@
   OS << "const unsigned int " << TargetName << "DFAStateEntryTable[] = {\n";
 
   // Multiply i by 2 since each entry in DFAStateInputTable is a set of
-  // two numbers
+  // two numbers.
   for (unsigned i = 0; i < states.size(); ++i)
     OS << StateEntry[i] << ", ";
 
@@ -329,7 +329,7 @@
 
 
   //
-  // Emit DFA Packetizer tables if the target is a VLIW machine
+  // Emit DFA Packetizer tables if the target is a VLIW machine.
   //
   std::string SubTargetClassName = TargetName + "GenSubtargetInfo";
   OS << "\n" << "#include \"llvm/CodeGen/DFAPacketizer.h\"\n";
@@ -350,11 +350,11 @@
                                   Record *ItinData,
                                   unsigned &NStages,
                                   raw_ostream &OS) {
-  // Collect processor itineraries
+  // Collect processor itineraries.
   std::vector<Record*> ProcItinList =
-                       Records.getAllDerivedDefinitions("ProcessorItineraries");
+    Records.getAllDerivedDefinitions("ProcessorItineraries");
 
-  // If just no itinerary then don't bother
+  // If just no itinerary then don't bother.
   if (ProcItinList.size() < 2)
     return;
   std::map<std::string, unsigned> NameToBitsMap;
@@ -364,7 +364,7 @@
     Record *Proc = ProcItinList[i];
     std::vector<Record*> FUs = Proc->getValueAsListOfDefs("FU");
 
-    // Convert macros to bits for each stage
+    // Convert macros to bits for each stage.
     for (unsigned i = 0, N = FUs.size(); i < N; ++i)
       NameToBitsMap[FUs[i]->getName()] = (unsigned) (1U << i);
   }
@@ -372,22 +372,22 @@
   const std::vector<Record*> &StageList =
     ItinData->getValueAsListOfDefs("Stages");
 
-  // The number of stages
+  // The number of stages.
   NStages = StageList.size();
 
-  // For each unit
+  // For each unit.
   unsigned UnitBitValue = 0;
 
-  // Compute the bitwise or of each unit used in this stage
+  // Compute the bitwise or of each unit used in this stage.
   for (unsigned i = 0; i < NStages; ++i) {
     const Record *Stage = StageList[i];
 
-    // Get unit list
+    // Get unit list.
     const std::vector<Record*> &UnitList =
       Stage->getValueAsListOfDefs("Units");
 
     for (unsigned j = 0, M = UnitList.size(); j < M; ++j) {
-      // Conduct bitwise or
+      // Conduct bitwise or.
       std::string UnitName = UnitList[j]->getName();
       assert(NameToBitsMap.count(UnitName));
       UnitBitValue |= NameToBitsMap[UnitName];
@@ -400,38 +400,38 @@
 
 
 //
-// Run the worklist algorithm to generate the DFA
+// Run the worklist algorithm to generate the DFA.
 //
 void DFAGen::run(raw_ostream &OS) {
   EmitSourceFileHeader("Target DFA Packetizer Tables", OS);
 
-  // Collect processor iteraries
+  // Collect processor iteraries.
   std::vector<Record*> ProcItinList =
     Records.getAllDerivedDefinitions("ProcessorItineraries");
 
   //
-  // Collect the instruction classes
+  // Collect the instruction classes.
   //
   for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
     Record *Proc = ProcItinList[i];
 
-    // Get processor itinerary name
+    // Get processor itinerary name.
     const std::string &Name = Proc->getName();
 
-    // Skip default
+    // Skip default.
     if (Name == "NoItineraries")
       continue;
 
-    // Sanity check for at least one instruction itinerary class
+    // Sanity check for at least one instruction itinerary class.
     unsigned NItinClasses =
       Records.getAllDerivedDefinitions("InstrItinClass").size();
     if (NItinClasses == 0)
       return;
 
-    // Get itinerary data list
+    // Get itinerary data list.
     std::vector<Record*> ItinDataList = Proc->getValueAsListOfDefs("IID");
 
-    // Collect instruction classes for all itinerary data
+    // Collect instruction classes for all itinerary data.
     for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
       Record *ItinData = ItinDataList[j];
       unsigned NStages;
@@ -441,7 +441,7 @@
 
 
   //
-  // Run a worklist algorithm to generate the DFA
+  // Run a worklist algorithm to generate the DFA.
   //
   DFA D;
   State* Initial = new State;
@@ -454,7 +454,7 @@
   WorkList.push_back(Initial);
 
   //
-  // Worklist algorithm to create a DFA for processor resource tracking
+  // Worklist algorithm to create a DFA for processor resource tracking.
   // C = {set of InsnClasses}
   // Begin with initial node in worklist. Initial node does not have
   // any consumed resources,
@@ -479,14 +479,14 @@
       std::set<unsigned> NewStateResources;
       //
       // If we haven't already created a transition for this input
-      // and the state can accommodate this InsnClass, create a transition
+      // and the state can accommodate this InsnClass, create a transition.
       //
       if (!D.getTransition(current, InsnClass) &&
           current->canAddInsnClass(InsnClass, NewStateResources)) {
         State* NewState = NULL;
 
         //
-        // If we have seen this state before, then do not create a new state
+        // If we have seen this state before, then do not create a new state.
         //
         //
         std::map<std::set<unsigned>, State*>::iterator VI;
@@ -507,6 +507,6 @@
     }
   }
 
-  // Print out the table
+  // Print out the table.
   D.writeTableAndAPI(OS, TargetName);
 }
diff --git a/utils/TableGen/DFAPacketizerEmitter.h b/utils/TableGen/DFAPacketizerEmitter.h
index f180fc6..9a13e78 100644
--- a/utils/TableGen/DFAPacketizerEmitter.h
+++ b/utils/TableGen/DFAPacketizerEmitter.h
@@ -25,14 +25,14 @@
 namespace llvm {
 //
 // class DFAGen: class that generates and prints out the DFA for resource
-// tracking
+// tracking.
 //
 class DFAGen : public TableGenBackend {
 private:
   std::string TargetName;
   //
   // allInsnClasses is the set of all possible resources consumed by an
-  // InstrStage
+  // InstrStage.
   //
   DenseSet<unsigned> allInsnClasses;
   RecordKeeper &Records;